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MAC Fundamentals

Multiply-Accumulate (MAC) Unit

The atomic operation in AI: result = (a × b) + c

// Verilog MAC unit
module mac_unit (
  input signed [7:0] a, b,
  input signed [15:0] c,
  output reg signed [15:0] result,
  input clk
);
  always @(posedge clk) begin
    result <= (a * b) + c;  // One cycle latency
  end
endmodule

Why It Matters

✅ One 8-bit × 8-bit multiply + accumulate per cycle
✅ Pipeline-able: 1 new result every cycle
✅ Multiply-Accumulate = fundamental NN operation

Day 7: Scale from one MAC to thousands in a systolic array.