Question 1

What is UCIe (Universal Chiplet Interconnect Express)?

Accepted Answer

UCIe is an open, industry-standard die-to-die interconnect specification established by the UCIe Consortium. It defines a complete 3-layer architecture (Protocol Layer, Die-to-Die Adapter, and Physical Layer) enabling heterogeneous chiplets from different foundries and process nodes to communicate with ultra-high bandwidth, low latency, and superior power efficiency.

Question 2

What are the three architectural layers of UCIe?

Accepted Answer

1) Protocol Layer: Maps higher-level protocols such as PCIe 6.0/7.0, CXL 2.0/3.0, or raw streaming protocols onto standard 256B/68B FLITs; 2) Die-to-Die Adapter: Manages link state, flow control, and optional CRC generation with replay buffers across the FDI (FLIT-aware Die-to-Die Interface); 3) Physical Layer (PHY): Transmits data over high-speed mainband lanes and coordinates link training, calibration, and power states over a robust out-of-band sideband channel.

Question 3

How does Standard Packaging compare to Advanced Packaging in UCIe?

Accepted Answer

Standard packaging uses conventional organic substrates with bump pitches between 100-130µm and 16 data lanes per module (reaches up to 25mm). Advanced packaging uses high-density silicon bridges or interposers (such as Intel EMIB or TSMC CoWoS) with micro-bump pitches of 25-55µm, 64 data lanes per module, delivering over 1.5-3.2 Tbps/mm of shoreline bandwidth density with sub-0.25 pJ/bit energy efficiency.

Max Data Rate:	32 Gbps / pin
Shoreline Density:	~1.5 – 3.2 Tbps / mm
Energy Efficiency:	~0.25 pJ / bit
FDI Interface:	FLIT-aware D2D Interface

⚙️ Packaging & Camera Views

UCIe 3D Chiplet Explorer — Die-to-Die Interconnect Laboratory