AMBA APB Protocol Specification

The Advanced Peripheral Bus (APB) is part of the ARM Advanced Microcontroller Bus Architecture (AMBA) family. It is a low-cost, low-power interface optimized for minimal power consumption and reduced interface complexity.

                        Key Characteristics
                        Non-Pipelined: Simple request/response model.
Synchronous: All signals timed to rising edge of PCLK.
Two-Cycle Min: Every transfer takes at least 2 cycles (Setup + Access).
Low Bandwidth: Ideal for configuration registers and low-speed peripherals (UART, Timer, GPIO).

                    

                        Terminology
                        Requester: The Bridge/Master initiating the transfer.
Completer: The Peripheral/Slave responding.
Bridge: Converts high-performance bus (AHB/AXI) to APB.

                    

1. Signal Descriptions (Chapter 2)

The APB interface has evolved from APB2 to APB5. Below is the complete signal list.

Signal	Source	Description
`PCLK`	Clock	Global Clock source. Rising edge active.
`PRESETn`	Reset	System Reset. Active LOW.
`PADDR`	Requester	Address Bus (up to 32-bit).
`PSELx`	Requester	Select signal for each Completer.
`PENABLE`	Requester	Enable. Indicates 2nd cycle of transfer.
`PWRITE`	Requester	Direction. High=Write, Low=Read.
`PWDATA`	Requester	Write Data Bus.
`PRDATA`	Completer	Read Data Bus.
`PREADY`	Completer	Ready. Used to extend transfer (Wait States).
`PSLVERR`	Completer	Error. Indicates transfer failure.
`PPROT`	Requester	Protection level (Privileged/Secure/Instruction).
`PSTRB`	Requester	Write Strobe (Sparse data writes).
`PWAKEUP`	Requester	Indicates activity to wake up clock domain (APB5).
`PAUSER`	Requester	User-defined attribute for request (APB5).
`PNSE`	Requester	Realm Management Extension (RME) Security (APB5).
`P*CHK`	Both	Parity Check signals for all buses (APB5).

2. Operating States (Chapter 4)

The APB state machine is the core of the protocol. It is simple and robust.

State 1: IDLE

The default state. PSEL and PENABLE are both LOW. No transfer is occurring.

State 2: SETUP

The bus moves here when a transfer is required.
Actions: Assert PSEL. Set PADDR and PWRITE. If Write, set PWDATA.
Duration: Exactly ONE clock cycle. PENABLE remains LOW.

State 3: ACCESS

The enable phase.
Actions: Assert PENABLE. PSEL remains HIGH.
Exit Condition: Sample PREADY from Completer.

If PREADY = 0: Stay in ACCESS (Wait State). Signals must remain stable.
If PREADY = 1 and no new transfer: Transfer complete. Go to IDLE.
If PREADY = 1 and new transfer pending: Transfer complete. Go immediately to SETUP (Back-to-Back).

3. Transfer Types (Chapter 3)

3.1 Write Transfer

Cycle 1 (Setup): Requester drives Address, Write Data, Write Signal, and Select.
Cycle 2 (Access): Requester asserts Enable. Completer samples data on rising edge of clock if Ready is high.

3.2 Read Transfer

Cycle 1 (Setup): Requester drives Address, Select. PWRITE is Low.
Cycle 2 (Access): Requester asserts Enable. Completer drives Read Data onto PRDATA. Requester samples data at end of cycle if Ready is high.

3.3 Wait States

The Completer can assert PREADY = LOW to hold the bus in the ACCESS state. This effectively freezes all control signals until the peripheral is ready to complete the task.

3.4 Error Response (PSLVERR)

Used to indicate an invalid transfer (e.g., writing to a read-only register). PSLVERR is only valid during the last cycle of an APB transfer (when PSEL, PENABLE, and PREADY are all HIGH).

4. APB5 Enhancements (Modern Features)

1. Parity Protection (Chapter 5)

For safety-critical systems (ISO 26262), APB5 adds interface protection. Signals like PADDR, PWDATA, and control signals are accompanied by Check signals (e.g., PADDRCHK). Odd parity is standard.

2. Wake-up Signaling

PWAKEUP indicates activity on the interface, allowing clock controllers to restore power/clocks to the peripheral subsystem before the transaction begins.

3. User Signals

PAUSER, PWUSER, etc., allow designers to add custom sideband signals to the protocol without violating the spec.