HomeDay 18

Advanced SVA

Complex Temporal Patterns

repeat: Signal true for N consecutive cycles.

// data_valid must be true for 4 cycles straight property data_burst; @(posedge clk) data_valid[*4] |-> data_out == expected; endproperty // [*N] = exactly N times // [*N:M] = N to M times // [+] = one or more times // [*] = zero or more times

first_match & throughout

first_match: Match first occurrence. throughout: Condition holds across the sequence.

// First time req high, ack follows within 3 cycles property first_req; @(posedge clk) first_match(req) |-> ##[1:3] ack; endproperty // addr_valid must hold throughout the transfer property addr_stable; @(posedge clk) (req, addr_valid throughout) ##2 done; endproperty

Key Takeaways

Day 19: Assertion coverage and debugging.