SV Day 20 — Assertions in Testbenches

Binding Assertions

Assertions live in modules or interfaces, or in separate bind statements:

// Place assertions in a module
module fifo_assertions (
  input clk, reset,
  input [7:0] data_in, data_out,
  input wr_en, rd_en,
  input [3:0] count
);

  // Assert: count increments on write
  property wr_count;
    @(posedge clk) disable iff(reset)
      wr_en && ~rd_en |-> ##1 count > $past(count);
  endproperty
  assert property(wr_count);

endmodule

// Or bind assertions to existing modules
bind fifo fifo_assertions fifo_bind_inst (.*);

// In testbench
module fifo_tb();
  fifo #(.WIDTH(8), .DEPTH(16)) dut();
  // Assertions automatically active
endmodule

Controlling Assertions in Tests

Enable/disable specific assertions during certain phases:

initial begin
  // During reset, disable timing assertions
  $assertoff(0, dut.protocol_assertions);

  #100 reset = 0;

  // After reset, enable all assertions
  $asserton(0, dut.protocol_assertions);

  // Run test
  #10000 $finish;
end

Phase 4 Complete!

You now know: constraints, coverage, and assertions. Next: UVM framework.