Async FIFO Theory

The Asynchronous FIFO is used to safely transfer data between two different clock domains. The key challenge is calculating Full and Empty flags when the pointers (Write and Read) originate from different, asynchronous clocks.

Gray Code Pointers

To prevent metastability and multi-bit signal glitches, binary pointers are converted to Gray code before being synchronized. In Gray code, only one bit changes at a time.

Controls

Write Clock100 MHz
Read Clock50 MHz

Log

WRITE DOMAIN READ DOMAIN DUAL PORT RAM W_BIN 0000 BIN2GRAY W_PTR 0000 FULL LOGIC FF FF SYNC R2W 0000 FULL R_BIN 0000 BIN2GRAY R_PTR 0000 EMPTY LOGIC FF FF SYNC W2R 0000 EMPTY

SystemVerilog Implementation

// Top Level Async FIFO
module async_fifo #(
    parameter DSIZE = 8,
    parameter ASIZE = 4
)(
    input  logic wclk, wrst_n, winc,
    input  logic [DSIZE-1:0] wdata,
    output logic wfull,
    input  logic rclk, rrst_n, rinc,
    output logic [DSIZE-1:0] rdata,
    output logic rempty
);
    wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
    // Synchronizers, Memory, Pointers...
endmodule