EcrioniX Labs

CDC VERIFICATION LAB

Clock Domain Crossing & Metastability Analysis

Calculated MTBF
HIGH
Failures Detected
0

DOMAIN CONFIGURATION

SOURCE DOMAIN (A) 100 MHz
DESTINATION DOMAIN (B) 75 MHz

Analysis

Setup/Hold Violation: When Data changes inside the capture window of CLK_B, the FF output becomes METASTABLE (oscillating).

Solution: A multi-stage synchronizer allows time for the metastable state to settle to a valid '0' or '1' before propagation.

MTBF (Mean Time Between Failures): Increases exponentially with each flip-flop stage added.

LOGIC SCHEMATIC
DOMAIN A (SRC) DOMAIN B (DEST) SRC_FF CLK_A ASYNC PATH SYNC_1 CLK_B SYNC_2 SYNC_3 SAFE DATA
REAL-TIME WAVEFORMS
CLK A
CLK B
GLITCH
CLK_A
DATA_A
CLK_B
ASYNC_IN
SYNC_1
SYNC_OUT