CLOCK GATING ICG

Low Power Design: Glitch-Free Integrated Clock Gating

DYNAMIC POWER 0%

Relative to free-running clock

GATER CONFIGURATION

ARCHITECTURE

Standard Industry Cell. Uses a level-sensitive latch to filter glitches on the Enable line.

ENABLE SIGNAL OFF (GATED)

Click repeatedly to toggle enable.
Try toggling rapidly when Clock is HIGH!

WHY DO WE NEED A LATCH?

1. The Problem: In a simple CLK & EN gate, if EN changes while CLK is High, the output immediately changes. This creates narrow pulses or Glitches that can corrupt data downstream.

2. The Solution (ICG): An Integrated Clock Gating cell adds a Level-Sensitive Latch (active Low) before the AND gate.

When CLK=0, Latch is transparent. It captures EN.
When CLK=1, Latch is Opaque (Locked).

Result: The enable signal seen by the AND gate only changes when CLK is Low, ensuring clean, full pulses.

LOGIC SCHEMATIC

TIMING DIAGRAM

CLK_SRC ENABLE LATCH_Q GCLK_OUT

CLK

LAT

OUT