EcrioniX VLSI

The Fundamental Logic Gate

The CMOS (Complementary Metal-Oxide-Semiconductor) Inverter is the most basic building block of digital integrated circuits. It performs the logical NOT operation: inputting a 0 results in a 1, and vice versa.

1. Structure

It consists of two transistors connected in series between the supply voltage ($V_{DD}$) and ground ($GND$):

  • PMOS (Top): Connected to $V_{DD}$. It turns ON when the input is Low (0V). It acts as a "Pull-Up" network.
  • NMOS (Bottom): Connected to $GND$. It turns ON when the input is High ($V_{DD}$). It acts as a "Pull-Down" network.

2. Operation Principles

Input Low ($V_{in} = 0$)

  • PMOS: ON ($|V_{GS}| > |V_{tp}|$)
  • NMOS: OFF ($V_{GS} < V_{tn}$)
  • Result: Output pulled to $V_{DD}$ (Logic 1)

Input High ($V_{in} = V_{DD}$)

  • PMOS: OFF
  • NMOS: ON
  • Result: Output pulled to $GND$ (Logic 0)

3. Voltage Transfer Characteristic (VTC)

The VTC curve plots $V_{out}$ vs. $V_{in}$. Ideally, it's a sharp step function. In reality, there is a transition region where both transistors are partially ON, consuming **short-circuit power**.

\[ V_M = \frac{V_{DD} - |V_{tp}| + V_{tn} \sqrt{\beta_n / \beta_p}}{1 + \sqrt{\beta_n / \beta_p}} \]

The switching threshold ($V_M$) is where $V_{in} = V_{out}$. It is typically designed to be $V_{DD}/2$ by balancing the transistor sizes ($\beta_n \approx \beta_p$).

Input Control

Input Voltage ($V_{in}$) 0.0 V
GND (0) VDD (1)
Digital Mode (0/1)

Transistor Sizing (W/L)

PMOS Ratio ($\beta_p$) 2.0
NMOS Ratio ($\beta_n$) 1.0

Adjusting sizes changes the switching threshold ($V_M$). PMOS is usually wider to balance mobility.

Analysis

Output ($V_{out}$) 5.0 V
Region P:LIN, N:CUT
Short Circuit I 0.00 mA
VDD (5V) GND (0V) PMOS NMOS Vin Vout

Voltage Transfer Characteristic (VTC)