What is master-slave architecture in a D flip-flop?

A master-slave flip-flop uses two latches in series. The master (active when CLK=0) samples input and holds it. When CLK rises, the master locks and the slave becomes transparent, transferring the held value to Q. The result is a true edge-triggered register — D is only sampled on the rising edge.

What happens when setup time is violated?

When D changes within the setup window before the clock edge, the master latch sees a partially-transitioned input. The flip-flop output Q may become metastable — floating between 0 and 1 — potentially propagating errors to downstream logic.

What is clk-to-Q delay?

Clk-to-Q (T_cq) is the propagation delay from the rising clock edge to when the output Q reaches a valid logic level. It is a fundamental parameter in STA: the total combinational path budget equals T_clk minus T_cq (launch) minus T_setup (capture).

When should async reset be used vs sync reset?

Async reset is preferred when the design must come out of reset reliably regardless of clock state — for example, a power-on reset or a brown-out recovery. Sync reset is preferred when reset must be glitch-free and easy for STA tools to analyze. Async reset must always be released synchronously (ARSR pattern) to avoid metastability.

D Flip-Flop Internals – Master-Slave Architecture & Timing

1. Edge-Triggered Sampling

A D flip-flop (DFF) is the fundamental storage element of synchronous digital design. It captures the value of its data input D at the moment of a clock edge and holds that value until the next edge. Unlike a latch, which is transparent for an entire clock phase, the DFF responds only to a razor-thin event — the rising (or falling) edge of CLK.

This edge-triggering property is what makes synchronous design analyzable. Static Timing Analysis (STA) tools can characterize every data path as "launched at one edge, captured at the next" and verify setup and hold constraints against a single, well-defined reference point.

2. Master-Slave Architecture

Internally, a positive-edge-triggered D flip-flop is implemented as two back-to-back latches:

Master latch — transparent when CLK=0, holds value when CLK=1
Slave latch — transparent when CLK=1, holds value when CLK=0

During the CLK=0 phase, the master latch is open and tracks D continuously. When CLK rises, the master locks — it captures the current value of D and becomes opaque. Simultaneously, the slave latch opens and passes the master's held value to Q. The result is that Q changes to reflect D at the moment of the clock edge, and holds that value for the full clock period.

CLK Phase	Master Latch	Slave Latch	Output Q
CLK = 0	Transparent — tracks D	Opaque — holds Qm	Holds previous Q
CLK ↑ (rising)	Locks — captures D instantly	Opens — passes Qm to Q	Q ← D (captured)
CLK = 1	Opaque — D changes ignored	Transparent — passes Qm	Stable at captured value
CLK ↓ (falling)	Opens again for next cycle	Locks	Q held until next rising edge

This two-phase handoff is why the DFF is truly edge-sensitive: D is only "visible" to the output path for the instant the master locks and slave opens simultaneously — the rising edge window.

3. Setup Time and Hold Time

The flip-flop can only guarantee a correct capture if the data signal D is stable around the clock edge. Two timing parameters define the required stability window:

Setup Time (T_su)

Minimum time D must be stable before the clock edge. If D changes within this window, the master latch sees an incompletely transitioned input and may capture a glitch.

Hold Time (T_h)

Minimum time D must remain stable after the clock edge. Changing D too soon disrupts the master latch as it is locking, before the master output is fully committed.

Clk-to-Q (T_cq)

Time from clock edge to when Q reaches a valid output level. This is the flip-flop's own propagation delay and is subtracted from the timing budget for the downstream combinational path.

T_clk > T_cq + T_comb + T_setup Setup constraint: data must arrive before capture edge

T_comb > T_hold − T_cq Hold constraint: combinational delay must not be too fast

Metastability: When D violates setup or hold time, the flip-flop enters a metastable state — Q floats between 0 and 1, neither a valid high nor a valid low. The flip-flop will eventually resolve to one of the two states, but the time to resolve (T_MET) is unbounded in theory. If T_MET exceeds the remaining clock period, the metastable output propagates to downstream logic and corrupts state. This is the fundamental mechanism behind Clock Domain Crossing (CDC) failures.

4. RTL Coding Variants

The D flip-flop maps to different SystemVerilog patterns depending on the reset style, clock enable, and initial value requirements:

Plain Register (No Reset)

always_ff @(posedge clk)
  q <= d;

Synchronous Reset

always_ff @(posedge clk)
  if (!rst_n) q <= '0;
  else        q <= d;

// Reset is sampled at CLK edge — STA treats it as data.
// Preferred for scan test and simulation predictability.

Asynchronous Reset (ARSR pattern)

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) q <= '0;
  else        q <= d;

// Assert async (immediate), de-assert synchronously via rst_sync.
// negedge in sensitivity list = active-low async reset.

Clock Enable

always_ff @(posedge clk or negedge rst_n)
  if (!rst_n)   q <= '0;
  else if (en)  q <= d;   // ICG inferred or explicit CE port
  // else: q holds — no else needed, register holds

Set and Reset (Parameterized)

module dff_sr #(parameter RESET_VAL = 1'b0) (
  input  logic clk, rst_n, set_n, d,
  output logic q
);
  always_ff @(posedge clk or negedge rst_n or negedge set_n)
    if      (!rst_n) q <= 1'b0;
    else if (!set_n) q <= 1'b1;
    else             q <= d;
endmodule

5. Timing Parameters Summary

Parameter	Symbol	Typical Value (28nm)	Violation Consequence
Setup time	T_su	50–100 ps	Metastability or wrong capture
Hold time	T_h	5–30 ps	Metastability, data corruption
Clk-to-Q	T_cq	60–120 ps	Reduces comb path budget
Async reset recovery	T_rec	50–80 ps	Async de-assert metastability
Async reset removal	T_rem	20–40 ps	Async assert metastability

6. Common RTL Pitfalls

Plain always instead of always_ff — synthesizer may map to latch if sensitivity list is incomplete
Mixing async reset and sync enable improperly — reset and enable priority must be explicit in the if/else chain
Async reset without synchronizer — releasing async reset without an ARSR synchronizer causes metastability on de-assertion
Initial values without reset — FPGA synthesis supports initial blocks; ASIC synthesis does not — always use explicit resets
Non-blocking inside combinational block — use <= only in always_ff; use = in always_comb

Interactive Lab — Master-Slave Timing Simulator

Toggle D near the clock edge to trigger setup/hold violations. Watch the master and slave latch states update in the schematic and waveform panel.

Controls

Data (D) 0

Clock (CLK) LOW

Speed 3

1 8

MASTER: OFF SLAVE: OFF Q = 0 OK

Master-Slave Topology

CLK D Qm Q

Frequently Asked Questions

A master-slave flip-flop uses two latches in series. The master (active-low clock) tracks D during CLK=0 and locks on the rising edge. The slave (active-high clock) opens on the rising edge and passes the master's captured value to Q. Only D's value at the exact clock edge is transferred — making the DFF truly edge-triggered.

When D changes within the setup window before the clock edge, the master latch captures an incompletely transitioned signal. The flip-flop output Q enters a metastable state — neither a valid HIGH nor LOW — and will eventually settle, but the settlement time may exceed the available clock period, propagating a glitch to downstream logic.

Clk-to-Q (T_cq) is the propagation delay from the rising clock edge to when output Q reaches a valid logic level. In STA, the launch flip-flop's T_cq reduces the time available for combinational logic: budget = T_clk − T_cq(launch) − T_setup(capture). A slow flip-flop directly tightens the available combinational path.

Async reset is preferred when the design must come out of reset reliably regardless of clock state — power-on reset, brown-out recovery, or when no clock is guaranteed. Sync reset is preferred when reset must be glitch-free and easy for STA to analyze. Critical rule: async reset must always be de-asserted synchronously (ARSR pattern) to prevent metastability on release.

The D Flip-Flop in ASIC Physical Design

In ASIC physical design, the D flip-flop is the fundamental building block of the clock tree and timing infrastructure. A 28nm design may contain 2–20 million flip-flops distributed across the die. The standard cell library offers multiple DFF variants characterized for different use cases: standard drive strength (for typical fanout paths), high drive strength (for cells with heavy capacitive loads), clock-enable variants (SDFF — scan-enabled DFF with MUX on D input), and scan-chain variants (SDFQ with scan_enable pin for DFT). The synthesizer selects among these based on timing requirements and power targets.

Clock tree synthesis (CTS) is the physical design step that distributes the clock signal from the PLL output to every flip-flop's CLK pin with balanced delay and minimum skew. The CTS algorithm inserts clock buffers in a tree topology — the root buffer drives several layer-1 buffers, each of which drives layer-2 buffers, and so on until individual flip-flop CLK pins are reached. A balanced tree ensures that all flip-flops in the same clock domain see the clock edge at nearly the same time. In 7nm designs, the target clock skew is typically under 20–30 ps across the full chip. Achieving this requires careful buffer sizing, systematic wire length balancing, and sometimes deliberate useful skew insertion to fix timing violations.

Power consumption from flip-flops comes from two sources: the clock tree itself (which toggles every cycle regardless of data) and the data-capture activity (which depends on how often D differs from Q). In power-intensive designs, clock gating (ICG cells on the clock tree) reduces the first component, and clock enable coding (keeping D==Q when no new data is present) reduces the second. Flip-flop power dominates in narrow-width datapaths where the flip-flop area is comparable to the combinational logic area, but is dominated by combinational power in wide datapaths like 512-bit buses and cache arrays.

For design-for-test (DFT), every flip-flop is typically connected into a scan chain. During manufacturing test, the scan enable (SE) pin is asserted, converting each SDFF into a simple shift register stage. Test patterns are shifted in, the chip is momentarily operated in functional mode (one capture cycle), then the captured data is shifted out and compared to expected values. A complete chip test requires covering all possible stuck-at and transition faults, which requires thousands to millions of test vectors. The scan insertion tool (Synopsys DFT Compiler or Cadence Encounter DFT) automatically inserts mux-before-flip-flop (MBF) scan cells and generates the scan chain connections, outputting both the modified netlist and the test access point (TAP) controller RTL.

D Flip-FlopInternals