EcrioniX VLSI

Physical Verification Basics

1. Design Rule Check (DRC)

DRC ensures your layout can actually be manufactured. It checks geometric constraints imposed by the foundry's lithography process.

  • Min Width: Wires too thin may break during fabrication (Open circuit).
  • Min Spacing: Wires too close may bridge together (Short circuit).
  • Enclosure: Vias must be fully covered by metal to ensure good contact.

2. Layout Versus Schematic (LVS)

LVS verifies that the physical layout corresponds exactly to the electrical schematic (netlist). It extracts devices (transistors, resistors) and connections from the shapes and compares them graph-to-graph.

Common LVS Errors: Shorted power rails (VDD/GND), open nets, or swapped inputs.

Tech Node Config

Process Node 180 nm
180nm90nm45nm
Min Width:3 units
Min Space:3 units

Layer Palette

DRC Violations

> System Ready.
> Draw shapes to check rules.
Mode: DRAWING (METAL 1)

LVS Challenge

LVS requires matching a complex netlist graph.
Coming Soon: An interactive CMOS Inverter routing challenge.