FIFO Depth Calculation

A **First-In-First-Out (FIFO)** buffer is used to safely transfer data between two modules operating at different speeds or clock domains. The critical design parameter is the **Depth**: how many slots are needed to prevent data loss (overflow) during a "burst" of writes when the reader is slower.

1. The Core Problem: Burst vs. Average

In steady state, the average Read rate must equal the average Write rate, or the FIFO will eventually overflow or underflow. However, data often arrives in **Bursts**. The FIFO must be deep enough to store the excess data that accumulates during the burst while the reader catches up.

2. Synchronous FIFO (Same Clock)

Even with the same clock, if the Writer sends data every cycle for a burst ($B$) but the Reader can only read every 2nd or 4th cycle (due to backpressure or protocol), a FIFO is needed.

3. Asynchronous FIFO (Clock Domain Crossing)

When crossing clock domains (e.g., 100MHz CPU to 50MHz Peripheral), we calculate based on the time it takes to write the burst vs. the time it takes to read during that same period.

• Worst Case Scenario: The writer sends a maximum burst ($B$) as fast as possible (Back-to-back cycles).
• The reader reads continuously but at its own slower pace.
• Depth Required = (Data Written) - (Data Read during the burst time).