Finite State Machines (FSM)

A Finite State Machine is a computation model used to design sequential logic circuits. It conceives the system as being in one of a finite number of states at any given time. The FSM transitions from one state to another in response to external inputs and produces outputs.

1. Moore Machine

Named after Edward F. Moore, this architecture defines the outputs solely based on the Current State.

• Output Equation: \( Y = f(S) \)
• Characteristics: The output is synchronous with the state. Changes in input do not affect the output until the next clock edge triggers a state transition.
• Pros: Safer design. Glitches on input lines do not propagate to the output. Easier to analyze timing.
• Cons: Often requires more states than Mealy machines. The output response is delayed by one clock cycle relative to the input change.

2. Mealy Machine

Named after George H. Mealy, this architecture determines the output based on both the Current State AND the Current Input.

• Output Equation: \( Y = f(S, I) \)
• Characteristics: The output is asynchronous relative to the clock. If the input changes, the output can change immediately within the same clock cycle.
• Pros: Faster response time (doesn't wait for clock). Often requires fewer states to implement the same logic.
• Cons: Input glitches pass directly to the output. Combinational path delays can be longer, potentially reducing max frequency.

3. Comparative Analysis