Low Power RTL Design Masterclass

1. The Physics of Power

To optimize power, we must first define it. In a CMOS circuit, power consumption is split into two categories: Dynamic and Static.

\[ P_{total} = \underbrace{\alpha C V_{dd}^2 f}_{Dynamic} + \underbrace{I_{leak} V_{dd}}_{Static} \]

Activity Factor (\(\alpha\)) How often signals toggle. This is the primary target for RTL designers.
Capacitance (\(C\)) The physical size of wires and transistors. Optimized by cell sizing.
Voltage (\(V_{dd}\)) The supply level. Power has a quadratic relationship with voltage.
Frequency (\(f\)) The clock speed. Faster clocks consume more linear power.

2. Critical RTL Techniques

A. Architectural Clock Gating

Clock gating is the most efficient way to reduce dynamic power. By disabling the clock to a register when the data doesn't need to change, we eliminate unnecessary charging and discharging of the clock tree and the flip-flop internals.

Unoptimized (Power Hungry)

always_ff @(posedge clk) begin
  // Data toggles every cycle
  // even if enable is false!
  data_reg <= (en) ? next_data : data_reg;
end
                    

Optimized (Gated)

assign gated_clk = clk & en_latched;

always_ff @(posedge gated_clk) begin
  // Clock only toggles when en is active.
  // No power spent on idle cycles!
  data_reg <= next_data;
end
                    

B. Operand Isolation

In large combinational blocks (like multipliers), input signals may toggle many times before the final result is actually needed. Operand isolation uses a simple gate to "freeze" the inputs to these heavy blocks when their output is not being used.

// Freeze inputs to the multiplier when 'valid' is low
assign safe_a = a & {WIDTH{valid}};
assign safe_b = b & {WIDTH{valid}};

assign mult_out = safe_a * safe_b;
            

C. FSM Encoding: Gray vs. Binary

For state machines that transition linearly (0-1-2-3), using Gray Encoding ensures only one bit toggles per transition. In a 32-bit state machine, switching from binary `0111` to `1000` causes 4 toggles, whereas Gray code only causes 1. This reduces switching activity (\(\alpha\)) in the state register and the surrounding logic.

Low Power RTL Design

1. The Physics of Power

2. Critical RTL Techniques

A. Architectural Clock Gating

Unoptimized (Power Hungry)

Optimized (Gated)

B. Operand Isolation

C. FSM Encoding: Gray vs. Binary

Switching Activity Lab

Data Bus Transition

Transition Analysis

Conclusion