Understanding the Gate Level Netlist

In the VLSI design flow, the Gate Level Netlist is the pivotal bridge between abstract code (RTL) and physical reality (Silicon). It is the result of the Logic Synthesis process, where high-level behavioral descriptions (like Verilog `if-else` statements or `assign` blocks) are translated into a specific set of logic gates available in the foundry's standard cell library.

1. What is a Netlist?

A netlist is essentially a text-based representation of a circuit schematic. It defines:

• Instances: The specific logic gates used (e.g., `AND2X1`, `DFF_X4`).
• Nets (Wires): The electrical connections between these instances.
• Ports: The primary inputs and outputs of the design.

Unlike RTL, which describes what the circuit does, a netlist describes how the circuit is built using components. It removes ambiguity and is the definitive guide for the Place and Route (PnR) tools.

2. Standard Cell Libraries & Drive Strength

Synthesis tools map your code to a Standard Cell Library. A unique feature of netlists is the concept of Drive Strength. A simple logic function like "AND" might have multiple versions in the library:

• AND2_X1: Minimum size, low power, slow, drives short wires.
• AND2_X4: 4x larger size, higher power, fast, drives long wires or high capacitance loads.
• AND2_X8: Very large, used for clock trees or high-fanout nets.

The synthesis tool chooses the best size based on your timing constraints (clock frequency) and power budget.

3. The Synthesis Process

The conversion from RTL to Netlist involves three main steps:

A. Translation

The tool converts Verilog keywords into generic boolean logic (GTECH). For example, `c = a + b` becomes a generic adder circuit.

B. Optimization

The tool manipulates the boolean logic to remove redundancy and flatten hierarchy. It tries to create the most efficient logic structure possible.

C. Technology Mapping

The generic logic is mapped to the specific standard cells provided by the foundry (e.g., TSMC 7nm or Intel 22nm). This is where timing arcs and wire delays are first estimated.

4. Netlist formats

While Verilog (`.v`) is the most common format for netlists, you might also encounter:

• EDIF: Electronic Design Interchange Format (Older).
• VHDL: Used in some legacy or FPGA flows.
• SPICE: A transistor-level netlist used for analog simulation, which is even lower level than gate-level.

5. Gate Level Simulation (GLS)

Why do we simulate the netlist if we already simulated the RTL?

RTL simulation is ideal; it assumes zero delay. Gate Level Simulation (GLS) includes timing delays. It helps catch:

• X-Propagation: Uninitialized states causing unknown values to ripple through the logic.
• Glitch Logic: Race conditions that RTL simulation misses.
• Timing Violations: Setup/Hold time errors on real paths.