Interactive Skew Balancing & Latency Visualization
Click on the yellow wires in the diagram to insert Buffers. Each buffer adds delay to that branch.
Latency: Total time taken for the clock signal to travel from the Source (PLL) to a Sink (Flip-Flop).
Skew: The difference in arrival times between two sinks. Ideally, Skew = 0.
"If Sink A gets the clock 100ps later than Sink B, we have 100ps of Skew. We fix this by adding buffers to the faster path (Sink B) to slow it down."