Shutting Down: The Power Gating Concept

As transistors shrink (scaling), leakage power becomes a dominant consumer of energy, even when the chip is idle. **Power Gating** is the most aggressive technique to reduce this static leakage by completely cutting off the power supply to inactive circuit blocks.

1. The Problem: Leakage Current

Even when a digital CMOS circuit is not switching (Idle), current flows from $V_{DD}$ to $GND$ due to **Subthreshold Leakage** ($I_{sub}$) and **Gate Oxide Leakage** ($I_{gate}$). In modern processes (7nm, 5nm), this can account for >40% of total power.

2. The Solution: Sleep Transistors

Power gating inserts a large, high-threshold voltage ($High-V_{th}$) transistor in series with the logic block and the power rail. This transistor acts as a switch.

• Header Switch (PMOS): Placed between true $V_{DD}$ and the circuit's virtual $V_{DD\_V}$. Used for high-side gating.
• Footer Switch (NMOS): Placed between true $GND$ and the circuit's virtual $GND\_V$. Used for low-side gating.
• Active Mode: The switch is ON (linear region), connecting the logic to the rail. It acts as a small resistor ($R_{on}$).
• Sleep Mode: The switch is OFF (cutoff region), breaking the path. Leakage is reduced exponentially because the sleep transistor is high-$V_{th}$.

3. Design Challenges (IR Drop & Wake-up)

IR Drop: When active, the sleep transistor is not a perfect wire. It has resistance ($R_{on}$). The current drawn by the logic ($I_{load}$) creates a voltage drop ($V_{drop} = I_{load} \times R_{on}$). This reduces the effective voltage seen by the logic ($V_{DD\_V} = V_{DD} - V_{drop}$), slowing it down.

In-Rush Current: When waking up, the virtual power rail capacitance must charge up quickly. This causes a massive spike in current from the main grid, which can cause voltage droops (noise) affecting other active blocks. Designers use "Daisy Chaining" to turn on sleep transistors gradually.

4. State Retention

When power is cut, standard flip-flops lose their data. If the block needs to resume where it left off, special **Retention Flip-Flops (RFF)** are used. These have a secondary low-leakage power supply to keep the data alive during sleep mode.