EcrioniX STA

Timing Constraints Explained

Static Timing Analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations without performing a simulation.

1. Setup Time ($T_{setup}$)

The minimum amount of time the data signal must be stable before the clock edge arrives.

Violation Condition: Data arrives too late.

Slack = Required Time - Arrival Time

Slack = (Tclk + Tskew - Tsetup) - (Tcq + Tlogic)

Fix: Reduce logic depth, improve cell drive strength, or slow down the clock (increase $T_{clk}$).

2. Hold Time ($T_{hold}$)

The minimum amount of time the data signal must remain stable after the clock edge arrives.

Violation Condition: Data changes too fast (Race Condition).

Slack = Arrival Time - Required Time

Slack = (Tcq + Tlogic) - (Tskew + Thold)

Fix: Add delay buffers to the data path. Slowing the clock does NOT fix hold violations.

Environment Parameters

Clock Period ($T_{clk}$) 10 ns
Combinational Delay ($T_{logic}$) 5.0 ns

Represents gate delays between Flops.

Clock Skew ($T_{skew}$) 0.0 ns

Positive: Capture clock arrives later.

Library Specs

$T_{setup}$
ns
$T_{hold}$
ns
$T_{cq}$ (Clk-to-Q)
ns
Reg-to-Reg Path
UFF1 Launch COMBO LOGIC UFF2 Capture 5.0ns

Timing Waveform

Launch CLK Capture CLK Data
Setup Check
+2.00 ns
Timing Met
Hold Check
+4.50 ns
Timing Met