SystemVerilog Data Types

SystemVerilog introduced a robust set of data types to bridge the gap between hardware description (Verilog) and high-level verification (C++/Java). Understanding these types is crucial for writing efficient RTL and effective Testbenches.

1. The 4-State Logic System

Unlike standard software programming, hardware simulation requires modeling more than just 0 and 1. SystemVerilog uses a 4-state logic system:

0: Logic Zero (Ground / Low)
1: Logic One (VCC / High)
X: Unknown / Uninitialized / Contentious. Represents a bug or unassigned value in simulation.
Z: High Impedance. Represents a disconnected wire or a tri-state buffer output.

2. The `logic` vs. `bit` Distinction

This is the most common interview question in SV.

logic (4-State)

Can store 0, 1, X, and Z. It is the preferred type for RTL design and connecting modules because it can model X-propagation (bugs) and unconnected ports (Z). It replaces the confusing `reg` vs `wire` distinction in most cases.

bit (2-State)

Can only store 0 and 1. It is the preferred type for Testbench components, Transaction packets, and C-interface modeling. It is faster to simulate.
Warning: If you assign X or Z to a `bit`, it silently converts to 0!

3. Integer Data Types

SystemVerilog adds C-like integer types for ease of verification:

byte: 8-bit signed integer (-128 to 127).
shortint: 16-bit signed integer.
int: 32-bit signed integer.
longint: 64-bit signed integer.
time: 64-bit unsigned (for simulation time).

Signed vs Unsigned: Types like `byte` are signed by default. This causes "Overflow" to wrap around to negative numbers (e.g., 127 + 1 = -128). This behavior must be understood to avoid arithmetic bugs.