UVM Architecture: The Verification Triad

Universal Verification Methodology (UVM) is the industry standard for verifying complex digital integrated circuits. At the heart of a UVM environment lies the UVM Agent, a container component that encapsulates the specific verification logic for a single interface (like PCIe, USB, or AXI). The agent typically contains three critical components: the Sequencer, the Driver, and the Monitor.

1. The UVM Sequencer (SQR)

The Sequencer acts as the traffic controller or arbiter of the verification environment. It does not generate data itself; rather, it manages the flow of data objects (transactions) known as Sequence Items.

• Arbitration: If multiple test sequences (scenarios) are running in parallel, the Sequencer decides which transaction goes next based on priority or round-robin algorithms.
• Routing: It routes the chosen transaction to the Driver via a TLM (Transaction Level Modeling) export.
• Analogy: Think of the Sequencer as the "Kitchen Expeditor" in a restaurant who takes orders from waiters (Sequences) and hands them to the chefs (Driver).

2. The UVM Driver (DRV)

The Driver is the active worker that interacts with the physical Device Under Test (DUT). It is the bridge between the abstract object-oriented world of UVM and the signal-level world of Verilog RTL.

• Pull Mechanism: The Driver initiates the data transfer. It calls seq_item_port.get_next_item(req) to fetch a transaction from the Sequencer.
• Pin Wiggling: It breaks down the abstract transaction (e.g., `write addr=0x10, data=0xFF`) into individual clock cycle signal toggles on the Virtual Interface (`vif`). This is where timing and protocol rules are enforced.
• Handshake: Once the pins are driven, it calls item_done() to signal the Sequencer that it is ready for the next job.

3. The UVM Monitor (MON)

The Monitor is a passive observer. Unlike the Driver, it never drives signals; it only samples them. It is present in both Active (driving) and Passive (monitoring only) agents.

• Sampling: It watches the Virtual Interface for signal changes synchronized to the clock.
• Reconstruction: It recognizes protocol patterns (start bit, data bits, stop bit) and reconstructs the pin wiggles back into a high-level `uvm_sequence_item`.
• Broadcasting: Once a transaction is captured, it broadcasts it via an Analysis Port. Subscribers like the Scoreboard (checks correctness) and Coverage Collector (checks completeness) listen to this port.

4. The Data Flow Summary

1. Sequence: Creates a randomized transaction object.
2. Sequencer: Queues the object.
3. Driver: Pulls object, drives pins on DUT.
4. DUT: Responds to pins.
5. Monitor: Observes pins, recreates object, sends to Scoreboard.
6. Scoreboard: Compares expected vs. actual result.