Multi-Domain Chip Design

1. Why Multiple Clock Domains?

Modern chips operate at different speeds for different subsystems:

• Processor core: 2-4 GHz (maximum frequency)
• Memory controller: 1 GHz (half speed for memory interface)
• Peripheral interface (USB, Ethernet): 100-500 MHz (dictated by external standards)
• Low-power domain: 100 MHz (sleep mode, minimal power)
• Analog/mixed-signal (PLL, ADC): Asynchronous (not synchronized to digital clocks)

Key insight: Running everything at maximum frequency wastes power. Different subsystems have different speed requirements, so independent clock domains allow power optimization.

2. Domain Classification

Independent Domains

Operate completely asynchronously. No strict timing relationship.

• USB interface (100 MHz external)
• Ethernet MAC (125 MHz from PHY)
• Analog PLL (frequency varies with supply/temp)

Derived Domains

Derived from a common clock through frequency dividers or multipliers. May have known phase relationships.

• Core @ 1 GHz
• Core/2 @ 500 MHz (derived, still needs CDC)
• Core/4 @ 250 MHz (derived)

Virtual Domains

Same physical clock, but treated as separate domains for design modularity.

• Processor pipeline stages clocked by the same clock but treated as separate domains for CDC verification

3. Multi-Domain Architecture Example

4. Clock Tree Design

Principle: Minimize Domain Crossings

Smart clock assignment minimizes CDC:

• Logic related to same data flow: Same clock domain
• Independent subsystems: Can be separate domains
• Shared resources (memory, buses): May require their own domain

Clock Distribution

Physical implementation:

• PLL/DLL: Generates clocks, usually one per domain
• Clock distribution network: Routes clocks to all flip-flops
• Clock gating: Local enable/disable per domain (for power management)
• Skew management: Keep skew within specification for each domain

5. Synchronization Strategy

CDC Map

Document every domain crossing:

From Domain	To Domain	Signal(s)	Type	Synchronizer
Core	Mem	write_enable, address	Control	Pulse sync
Core	USB	16-bit data	Data	Gray FIFO
USB	Core	interrupt_req	Control	2FF pulse sync
Mem	USB	status[7:0]	Status	Gray code
All	All	reset	Reset	Reset synchronizer

This map drives implementation, testing, and verification.

6. Integration Patterns

Pattern 1: Through Shared Memory

Multiple domains exchange data through a shared dual-port RAM with CDC on pointers (dual-clock FIFO).

Advantage: Decouples domains, natural buffering

Pattern 2: Through Synchronizers

Direct connections with explicit CDC logic (dual-FF, Gray code, pulse sync).

Advantage: Low latency, simple

Pattern 3: Through Interconnect Fabric

Shared bus with domain-crossing logic at interfaces.

Advantage: Scalable for many domains, centralized CDC

7. Timing Verification at Domain Boundaries

Each domain crossing must pass timing analysis:

• Input path: From source domain flip-flop to CDC module input
• CDC module: Internal timing (synchronizers must settle)
• Output path: From CDC module output to destination flip-flop

Critical constraint: Setup/hold on CDC module input may be violated intentionally (metastability window), but setup/hold elsewhere must be met.

8. Power Management Across Domains

Each domain can be power-gated independently:

• When USB not in use: clk_usb can be gated (0W)
• When processor sleeping: clk_core can be gated, but clk_sys remains for bus
• CDC logic must handle domains powering down/up dynamically

Challenges:

• Reset synchronizers may not work if target clock is gated (clock is needed to propagate reset)
• FIFOs may have stale data when a domain powers back up
• Solution: Flush FIFOs, reset pointers before power gating

9. Real-World Multi-Domain Examples

Example 1: Mobile Processor SoC

ARM processor, GPU, memory controller, radio, display interface:

• Processor: 2-3 GHz (frequency scaling)
• GPU: 600-900 MHz (frequency scaling)
• Memory: 800 MHz fixed
• Radio (LTE): 200 MHz asynchronous
• Display (MIPI): Variable (depends on resolution/refresh)
• Interconnect: 400 MHz backbone

CDC crossings: ~15+ major crossings (processor ↔ GPU, memory, radio, display). Each with Gray FIFO or synchronized handshake.

Example 2: Datacenter Network Switch

Multiple ports, each with its own interface clock:

• Port 1-48: 10 GbE (156.25 MHz clock from PHY)
• Fabric: 150 MHz shared interconnect
• CPU interface: 800 MHz (management)

CDC: 48 receive FIFOs (PHY clock → fabric), 48 transmit FIFOs (fabric → PHY clock), 1 CPU interface synchronizer. Total 97+ CDC interfaces.

10. Multi-Domain Verification Strategy

Layer 1: Unit tests (each CDC module individually)

Layer 2: Integration tests (each domain pair crossing)

Layer 3: Full system tests (all domains simultaneously with realistic traffic)

Layer 4: Formal verification (CDC lint + formal proofs on critical paths)

Layer 5: Silicon validation (post-tape-out testing at speed with real clocks)

11. Checklist: Multi-Domain Design

• ✅ Document all clock domains (names, frequencies, relationships)
• ✅ Create CDC map (every crossing identified)
• ✅ Implement CDC for each crossing (2FF, Gray, FIFO as appropriate)
• ✅ Synchronize reset to all domains
• ✅ Verify timing (setup/hold met, metastability handled)
• ✅ Formal verification (CDC lint, MTBF proofs)
• ✅ Test all PVT corners (especially slow-slow)
• ✅ Power management protocol (safe power gating with CDC)
• ✅ Document CDC design decisions (why each synchronizer choice)
• ✅ Design review sign-off (CDC expert approval)

Next (Days 11-15): FPGA CDC, tools, design patterns, debugging, and production verification.