Clock Domain Crossing

One of the hardest problems in chip design: safely passing data between clock domains without creating subtle bugs that appear randomly in silicon. This course teaches the theory, the patterns, and the verification techniques that every senior VLSI engineer must know.

▶ Start with Day 1 — The Metastability Problem

Who this is for: VLSI/chip designers working on multi-clock systems, verification engineers building CDC testbenches, and anyone who wants to understand why data corruption happens at clock domain boundaries. No prior CDC knowledge needed.

What you'll learn: Metastability theory, synchronizer architectures (2-FF, 3-FF, pulse), gray code, CDC formal verification, dual-clock FIFOs, practical design patterns, and how to catch CDC bugs before silicon.

PHASE 1

CDC Fundamentals

Day 1The metastability problem — why it happensLive Day 2The 2-flip-flop synchronizer — time-tested solutionLive Day 3Gray code — crossing multi-bit buses safelyLive Day 4Pulse synchronizers & handshake protocolsLive Day 5Dual-clock FIFOs — the cornerstone patternLive

PHASE 2

Advanced CDC Patterns

Day 6Data + handshake crossings — bus crossing safelyLive Day 7Reset synchronisation — the forgotten problemLive Day 8Control + data CDC — arbiters & arbitrationLive Day 9Clock gating across domainsLive Day 10Multi-clock domain hierarchiesLive

PHASE 3

CDC Verification & Tools

Day 11CDC testbenches — catching bugs before siliconLive Day 12Formal CDC verification — automated safety checksLive Day 13Commercial CDC tools (Synopsys SpyGlass, Cadence XCellent)Live Day 14CDC design review checklistLive Day 15🎉 Real-world case studies — bugs in production chipsLive

New lessons publish regularly. Pair with VLSI Design Hub, RISC-V course, and SystemVerilog verification.