CDC in FPGA

1. FPGA CDC Differences from ASIC

FPGAs have unique CDC characteristics:

• LUT-based logic: More timing variability than custom ASIC cells
• Routing delays: Longer, less predictable than hard cells
• FMAX variation: Can vary 5-10% per build
• Pre-built IP cores: Xilinx and Intel provide CDC primitives (advantage!)
• Constraints easier: FPGA tools more flexible with CDC constraints

Bottom line: CDC principles are identical, but FPGA tools provide more help.

2. Xilinx CDC Patterns

xpm_cdc_single (Single-Bit Crossing)

// Xilinx XPM single-bit synchronizer
xpm_cdc_single #(
  .DEST_SYNC_FF(2),        // Stages (2-3 typical)
  .INIT_SYNC_FF(0),        // Initial FF value
  .SIM_ASSERT_CHK(1)       // Simulation checking
) u_cdc_single (
  .clk_dst(clk_b),         // Destination clock
  .cdc_src(async_input),   // Source (async) signal
  .cdc_dst(sync_output)    // Synchronized output
);

// Usage: Replace manual 2FF with this. Xilinx optimizes placement.

xpm_cdc_gray (Gray Code Crossing)

Xilinx provides complete Gray code CDC with automatic encoding/decoding:

xpm_cdc_gray #(
  .WIDTH(8),                    // Pointer width
  .DEST_SYNC_FF(2)
) u_cdc_gray (
  .src_clk(clk_a),
  .src_in(write_ptr),           // Binary input
  .dest_clk(clk_b),
  .dest_out(write_ptr_gray)     // Gray output (synchronized)
);

// Advantage: Xilinx handles Gray conversion internally
// Disadvantage: Less control, harder to debug

xpm_cdc_pulse (Pulse Synchronization)

Xilinx provides toggle-latch + edge detection:

xpm_cdc_pulse #(
  .DEST_SYNC_FF(2),
  .REG_OUTPUT(1)
) u_cdc_pulse (
  .clk_src(clk_a),
  .pulse_src(input_pulse),      // Single-cycle pulse
  .clk_dst(clk_b),
  .pulse_dst(output_pulse)      // Synchronized pulse
);

3. Intel Quartus CDC Patterns

Intel (Altera) provides similar CDC IP in Quartus:

• altera_std_synchronizer: 2FF synchronizer
• altera_dcfifo_synchronizer: Dual-clock FIFO
• altera_multibit_sync: Multi-bit Gray code crossing

Usage is similar to Xilinx—instantiate, parametrize, connect.

4. FPGA-Specific CDC Constraints

Vivado Constraints (Xilinx)

// XDC constraints file for Xilinx Vivado

// CDC signals can violate setup/hold (intentional)
set_property KEEP_HIERARCHY SOFT [get_cells u_cdc_single]
set_property ASYNC_REG TRUE [get_cells u_cdc_single/cdc_dst*]

// Don't optimize away CDC stages (ISE compiler might try)
set_property IOB FALSE [get_cells u_cdc_single/cdc_dst_ff]

// Timing ignore (CDC crossing allowed to violate setup)
set_false_path -from [get_cells src_ff] -to [get_cells dst_ff1]

Quartus Constraints (Intel)

Similar approach using .sdc files (Synopsys constraints).

5. FPGA Synchronizer IP Recommendations

Recommendation: Use vendor IP when available. It's been tested, optimized, and handles tool constraints automatically.

6. FPGA CDC Verification

Simulation

Xilinx/Intel IP includes simulation models. Same testbench approaches as ASIC CDC.

Timing Analysis

FPGA timing reports show setup/hold violations at CDC boundaries (expected). Tools flag these and allow you to mark them as false paths.

Formal Verification

Limited FPGA formal CDC tools. Rely more on simulation + manual review.

7. Common FPGA CDC Mistakes

• ❌ Mistake: Using Vivado DSP/BRAM across clock domains without CDC
• ✓ Fix: Sync pointers with Gray code, data with dual-FF or FIFO IP
• ❌ Mistake: Not setting ASYNC_REG property in Vivado
• ✓ Fix: Mark CDC FFs with ASYNC_REG=TRUE to prevent optimization
• ❌ Mistake: Relying on placement to keep CDC FFs close (it won't)
• ✓ Fix: Use KEEP_HIERARCHY and ICLK constraints

8. Performance Implications

CDC adds latency (synchronization delay):

• 2FF synchronizer: 2-3 clock cycles of Clock B
• FIFO with sync: ~2-3 Clock B cycles for pointer sync
• Pulse sync: 2-3 Clock B cycles

Plan designs with this latency in mind. Real-time constraints may require optimized CDC (trade safety for speed).

9. Checklist: FPGA CDC

• ✅ Use vendor IP for standard CDC (xpm, altera_*)
• ✅ Set ASYNC_REG property on CDC FFs
• ✅ Mark CDC false paths in constraints
• ✅ Simulate with proper testbench (metastability injection)
• ✅ Review timing reports (ignore CDC setup violations)
• ✅ Account for sync latency in performance budget
• ✅ Test on real hardware (simulation ≠ silicon)

Next (Day 12): CDC tools and EDA integration.