1. Pattern 1: FIFO-Based Data Transfer
Use case: Transferring blocks of data (packets, bursts) between domains.
Implementation: Dual-clock FIFO with Gray code pointers.
Advantages:
- Natural decoupling of clock domains
- Absorbs clock frequency differences
- Automatic buffering
- FIFO handles synchronization internally
Disadvantages:
- 2-3 cycle sync latency
- Large area (FIFO RAM)
- Overkill for single-value transfers
When to use: Bulk data (USB packets, Ethernet frames, memory bursts)
2. Pattern 2: Handshake Protocol
Use case: Request-acknowledge communication between domains.
Implementation:
- Requester (Clock A): Assert req pulse
- Pulse sync to Clock B: req becomes req_b
- Responder (Clock B): Assert ack pulse when done
- Pulse sync to Clock A: ack becomes ack_a
- Requester (Clock A): Deassert req when ack received
Advantages:
- Simple, proven pattern
- Low area (pulse synchronizers only)
- Synchronization built in
Disadvantages:
- Slow (back-and-forth hand shaking)
- Latency: 4-6 clock cycles (req sync + ack sync)
When to use: Control signals, power management requests
3. Pattern 3: Level Synchronization with Edge Detection
Use case: Transfer status signals that can change at any time.
Implementation: Dual-FF on status signal, edge detector optional.
Advantages:
- Minimal latency (2-3 cycles)
- Simple
- Status always available
Disadvantages:
- Only works for stable signals (no rapid toggling)
- Metastability if input changes frequently
When to use: Status bits (FIFO full, device ready)
4. Pattern 4: One-Hot Encoding for Multi-Bit Control
Use case: Send encoded command across domains.
Implementation: Instead of binary encoding, use one-hot (only one bit set).
- Command 0: 0001 (bit 0)
- Command 1: 0010 (bit 1)
- Command 2: 0100 (bit 2)
- Command 3: 1000 (bit 3)
Advantage: Only one bit changes per command transition (like Gray code). Synchronize each bit independently with 2FF.
When to use: Multi-bit control with small number of values (3-8 commands)
5. Pattern 5: Resynchronization at Intermediate Stages
Use case: Data passes through multiple intermediate stages with different clocks.
Implementation: Resync at each clock domain boundary.
Example: Clock A → Clock B (via Gray FIFO) → Clock C (via Gray FIFO)
Disadvantage: Cascading latency (4-6 cycles per stage).
Mitigations: Plan for total latency, use deeper FIFOs.
6. Best Practice 1: Minimize CDC Crossing Points
Principle: The fewer signals crossing domains, the fewer bugs.
Techniques:
- Assign logic to same domain whenever possible
- Batch signals into FIFOs (reduces crossing count)
- Use multiplexing to reduce width of crossings
7. Best Practice 2: Use Vendor IP When Available
Principle: Don't reinvent the wheel. Xilinx/Intel synchronizer IP is tested.
Benefits:
- Verified correct (formal proofs)
- Optimized placement and timing
- Tool integration (constraints set automatically)
- Support and documentation
8. Best Practice 3: Document CDC Thoroughly
Required documentation:
- Clock domain diagram (names, frequencies, relationships)
- CDC crossing map (source, destination, signal, synchronizer type)
- MTBF targets and achieved values
- Timing constraints on CDC paths
- Formal verification results
- Test plan and coverage metrics
9. Best Practice 4: Formal Verification for Critical Paths
Principle: Not all CDC needs formal, but critical paths do.
Critical paths:
- Reset synchronization (affects entire system)
- FIFO pointers (data loss risk)
- High-frequency crossings (MTBF concerns)
- Automotive/aerospace applications (high reliability)
10. Common Anti-Patterns to Avoid
- ❌ Anti-pattern: Combinational logic from async input to output (glitch risk)
- ✓ Pattern: Synchronize first, then compute
- ❌ Anti-pattern: Multi-bit binary crossing without Gray code
- ✓ Pattern: Use Gray code for monotonic signals, FIFO for arbitrary data
- ❌ Anti-pattern: Single FF synchronizer for high-frequency
- ✓ Pattern: Use dual-FF or triple-FF based on MTBF requirement
- ❌ Anti-pattern: Reset without synchronization
- ✓ Pattern: Always synchronize async reset into each domain
11. Decision Tree: Choose Your Synchronizer
Question 1: Is signal asynchronous?
- No → Don't need synchronizer, use direct connection
- Yes → Go to Question 2
Question 2: How many bits?
- 1 bit → Go to Question 3
- Multi-bit → Go to Question 4
Question 3 (1-bit): Is it a pulse or level?
- Pulse → Use pulse synchronizer (toggle + edge detect)
- Level → Use 2FF synchronizer
Question 4 (Multi-bit): Is it monotonic (counter)?
- Yes → Use Gray code synchronizer
- No → Use dual-clock FIFO or one-hot encoding
12. Checklist: Design Patterns
- ✅ Use proven patterns (FIFO, handshake, level sync)
- ✅ Minimize CDC crossing points
- ✅ Use vendor IP (Xilinx, Intel, Cadence)
- ✅ Document CDC thoroughly (diagram, map, MTBF, constraints)
- ✅ Formal verification on critical paths
- ✅ Avoid anti-patterns (comb logic, binary multi-bit, single FF for high-freq)
- ✅ Design review by CDC expert
Next (Day 14): Debugging CDC issues and root cause analysis.