Dual-clock FIFO design from first principles — why a FIFO exists, a complete sync FIFO, why binary pointers cannot cross clocks, Gray code, full/empty math, overflow/underflow, synthesizable RTL, waveforms, and a live visual lab. Lessons are complete articles you can read without a login wall. Sign in if you want progress saved.
By the last lesson you should be able to size a FIFO from a burst, write a gated sync FIFO in Verilog, explain why a binary pointer cannot cross clocks, convert bin2gray / gray2bin on a whiteboard, draw a dual-clock block diagram, write the empty and two-MSB full equations, reset both domains safely, and defend overflow vs stall in an interview.
This is a long-form engineering article series, not a two-paragraph chip glossary. Each lesson includes definitions, worked numbers, waveforms with unrelated clocks, RTL you can paste into the EcrioniX Verilog simulator, failure modes, and an FAQ.
RTL students who have seen a FIFO symbol on a slide but never implemented pointers. Verification engineers who need a golden queue and SVA. FPGA designers instantiating a vendor FIFO who must still answer CDC questions. The sequence starts at rate matching — you do not need to already know Gray code.
Module 1 is the problem (bursts, clocks). Module 2 solves it on one clock so full/empty are unambiguous. Module 3 shows the CDC bug with binary 7→8, then Gray and register order. Module 4 is the production async FIFO (architecture, flags, RTL, reset). Module 5 is a live 8-deep lab plus interview scripts.
Clocks in WaveDrom use independent period and phase: wr_clk is not a divided rd_clk.
The lessons are published as complete technical articles. Sign in on the Premium hub if you want progress tracking. The Verilog simulator linked from each lesson is also free to use.
Yes in spirit: extra-MSB Gray pointers, 2FF synchronizers, empty by Gray equality in the read domain, full by inverting two Gray MSBs in the write domain, power-of-two depth, data in dual-port RAM.
Yes. FIFO/CDC questions are standard. You will practice overflow vs stall, why not 2FF a bus, and the exact full/empty formulas.
No. The visual lab and the browser Verilog simulator use two software clocks with different periods.