A live model of an 8-deep async FIFO: Gray pointers, 2FF delay on each crossing, extra-MSB full/empty. Watch occupancy, blocked writes, and conservative flags. This is the same pointer math as the RTL — not a cartoon queue that cheats.
Gold cells = occupied. Write pointer (cyan) and read pointer (violet). FULL/EMPTY use synchronized Gray, so they lag the true occupancy — that lag is the CDC tax.
After you watch a fill-to-full, copy the RTL from lesson 4.3 into the simulator with two always #period clocks. Open simulator →
1. Fill only. Set write every 1 tick, read every 6. Run until FULL. Confirm occupied cells equal 8 and further writes do not rotate data.
2. Drain only. After full, slow writes and speed reads. EMPTY should appear after the last beat plus 2FF, not in the same instant as the last write-side occupancy zero if you still have Gray in flight — watch the synced pointer, not just the gold cells.
3. Equal average rates. Write every 2, read every 2, but start with a phase offset (step write twice first). Occupancy should hover, not crash.
4. Reset mid-stream. Fill halfway, hit Reset. Both pointers and flags must return to empty, not a stuck FULL from a stale Gray.
This model does not simulate analog metastability, BRAM collision modes, or scan reset. It does delay Gray by two destination ticks so you feel conservative flags. Treat silicon as needing SDC, ASYNC_REG, and a scoreboard TB in addition to this animation.
An 8-deep async FIFO with Gray pointers, extra-MSB full/empty, and two-flop delay on each crossing — the same math as the RTL, not a cartoon queue.
The write Gray must be captured by two read-domain flops. Until then the reader legally believes the FIFO is still empty.
FULL rises using synchronized read Gray. Further write clocks must not overwrite gold cells. Blocked-write count should increase.
Copy lesson 4.3 into the simulator with always #4 and always #7 clocks, then fill and drain the same way.