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⚡ Silicon Architecture · 60 FPS Real-Time · FPGA & ASIC

Real-Time Image Processing Hardware Lab

Discover how silicon chips actually process streaming video without CPU overhead. Explore dual line buffers (BRAMs), 3×3 sliding window matrix registers, parallel adder trees, and real-time object tracking with synthesizable Verilog RTL.

Video Feed Source:
Silicon Kernel Engine:
LIVE HARDWARE OUTPUT STREAM
60.0 FPS · AXI4-Stream
PIXEL CLOCK: 124.8 MHz COORD: (240, 160)
THROUGHPUT: 1 Pixel / Cycle DRAM READS: 0 (Line-Buffer)
DETECTED OBJECT BOUNDING BOX: [X: 142, Y: 88, W: 64, H: 64]
CENTROID: (174, 120)
⚙️ INSIDE THE SILICON HARDWARE
RTL Pipeline Active
CYCLE-BY-CYCLE SILICON DATAFLOW (LIVE WIRES & BUSES) CLK: ⎍ TICK

Watch 8-bit pixels stream from camera into dual BRAM line buffers, latch into 3×3 shift registers, feed the parallel shift-add tree, and trigger the bounding box unit.

BUS EVENT: Cycle 1,048,576 · Streaming Raster Pixel (240, 160)
LATENCY: 1 Cycle / Pixel
STAGE 1: DUAL LINE BUFFER MEMORY (BRAM FIFO) ON-CHIP SRAM

Stores previous 2 image rows so the chip never re-reads from external memory. Real pixel byte values shift left each cycle.

Row Y-2 (FIFO 1):
Row Y-1 (FIFO 0):
Row Y (Stream):
STAGE 2 & 3: 3×3 SLIDING WINDOW & PARALLEL MAC ENGINE 1 CYCLE LATENCY
p00120
p01134
p02142
p10118
p11210
p12145
p20115
p21128
p22150
Gx (Horizontal Gradient): +84
Gy (Vertical Gradient): -32
Magnitude |Gx| + |Gy|: 116
Threshold Comparator (> 65): PASS (EDGE PIXEL)
STAGE 4: HARDWARE BOUNDING BOX COMPARATOR REGISTERS ZERO LATENCY
X_MIN
142
X_MAX
206
Y_MIN
88
Y_MAX
152
CYCLE TICK: 1,048,576
Throughput Rate
1 Pixel / Cycle
No stalls or memory contention
Clock Frequency
150 MHz
1080p @ 60 FPS = 124.8 MHz pixel clk
FPGA BRAM Utilization
2 × 18Kb BRAMs
Zero external DDR DRAM access
Multipliers / DSP Units
0 DSP Blocks
Power-efficient binary shifts (p << 1)
📐 SILICON MICRO-ARCHITECTURE BLOCK DIAGRAM
Synthesizable RTL Dataflow Pipeline

Complete Hardware Vision Pipeline Architecture

How pixel streams traverse dual on-chip BRAM line buffers, latch into the 3×3 sliding window register array, feed the 0-DSP shift-add arithmetic tree, and update the autonomous bounding box tracker without CPU intervention.

150 MHz Clock 1 Pixel / Cycle
ECRIONIX REAL-TIME SILICON VISION PIPELINE ARCHITECTURE ZERO DRAM BOTTLENECK · DUAL ON-CHIP BRAM FIFOs · 0 DSP MULTIPLIERS · 150 MHz SUSTAINED STAGE 0: INGEST MIPI / DVP RX Camera Sensor Core Raster Counters: current_x [9:0] current_y [8:0] Valid Range: 480×320 CLK: pixel_clk 150MHz STROBE: pixel_valid SYNC: hsync, vsync pixel_data [7:0] → STAGE 1: LINE BUFFERS DUAL BRAM FIFOs On-Chip Row Storage (SRAM) FIFO 0 (Row Y-1) 480 × 8-bit Dual-Port BRAM Wr: Pixel In · Rd: Delayed 1 Line Tap 1 Output [7:0] → FIFO 1 (Row Y-2) 480 × 8-bit Dual-Port BRAM Wr: FIFO 0 Rd · Rd: Delayed 2 Lines Tap 2 Output [7:0] → STAGE 2: WINDOW MATRIX 3×3 SHIFT MATRIX 9 Parallel D-Flip-Flops p00 p01 p02 p10 p11 p12 p20 p21 p22 ← Horizontal Shift on posedge CLK ← Parallel 9× 8-bit Bus Out → STAGE 3: PARALLEL MAC SHIFT-ADD TREE 0 Multipliers · Pure Logic Gates Gx: (p02 + 2·p12 + p22) - (p00 + 2·p10 + p20) [2× = << 1] Gy: (p20 + 2·p21 + p22) - (p00 + 2·p01 + p02) [2× = << 1] |Gx| + |Gy| (Manhattan) Threshold Comparator (> 65) ⚡ edge_strobe (1-bit pulse) STAGE 4: HARDWARE BOUNDING BOX UNIT Zero CPU Cycles · 4 Concurrent Hardware Comparators · VSYNC Frame Latch X_MIN COMPARATOR if (edge_strobe && x < x_min) x_min <= current_x; Reset State: 10'd1023 (Max) X_MAX COMPARATOR if (edge_strobe && x > x_max) x_max <= current_x; Reset State: 10'd0 (Min) Y_MIN COMPARATOR if (edge_strobe && y < y_min) y_min <= current_y; Reset State: 9'd511 (Max) Y_MAX COMPARATOR if (edge_strobe && y > y_max) y_max <= current_y; Reset State: 9'd0 (Min) FRAME END LATCH (VSYNC): Registers snapshot to output bus {out_xmin, out_xmax, out_ymin, out_ymax} & reset for next frame (0 CPU latency) STAGE 5: MIXER VIDEO OUTPUT OSD Engine & Display PHY OSD Box Engine Draws green target box Compares (X, Y) to [xmin, xmax, ymin, ymax] Video Multiplexer Mode 0: Raw Camera Mode 1: Sobel Edges Mode 2: Silicon Wafer + Live Bounding Box HDMI / DVP PHY 1080p @ 60 FPS Video Pixel Clk: 148.5 MHz Throughput: 1 Px/Clk Zero Pipeline Stalls Output: Video Stream [7:0] Tap 2 (Y-2) Tap 1 (Y-1) Tap 0 (Y Stream) 9× [7:0] edge_strobe (1b) (current_x, current_y) [19:0] [7:0] [38:0]
STAGE 1: LINE BUFFERS

Dual BRAM FIFOs (Zero DDR Overhead)

Traditional CPU or GPU image processing requires copying every video frame into external DDR DRAM, creating severe memory bus congestion. This FPGA pipeline stores only 2 horizontal scanlines (2 × 480 bytes = 960 Bytes) in dual on-chip Block RAMs.

On every clock tick, the newest pixel is written into FIFO 0, the read-out byte from FIFO 0 enters FIFO 1, and FIFO 1 outputs the pixel from 2 rows ago. This produces 3 vertically aligned pixels (Row Y, Row Y-1, Row Y-2) in parallel without DDR access.

On-Chip SRAM Required: 960 Bytes (< 1 BRAM tile)
STAGE 2: WINDOW MATRIX

3×3 Sliding Window (9 Shift Registers)

To compute 2D convolution, the chip needs a 3×3 pixel neighborhood surrounding each coordinate. Instead of reloading data, 9 D-Flip-Flops (p00 through p22) form a spatial shift matrix.

On each rising clock edge, the 3 new incoming bytes from the line buffer taps latch into column 2 (p02, p12, p22) while column 2 shifts into column 1, and column 1 into column 0. All 9 pixels are simultaneously available to combinational arithmetic gates every clock tick.

Register Count: 9 × 8-bit = 72 Flip-Flops
STAGE 3: PARALLEL MAC

0-DSP Multipliers (Bit-Shift Adder Tree)

The Sobel convolution kernels have fixed integer weights: [-1, 0, 1] and [-2, 0, 2]. In silicon, multiplying by 2 is accomplished by shifting wires left by 1 bit (p << 1), which requires zero transistors and zero DSP blocks.

A balanced 3-stage adder tree computes horizontal gradient Gx and vertical gradient Gy in parallel, adds absolute values |Gx| + |Gy| (Manhattan distance), and compares against the threshold in a single clock cycle.

Arithmetic Hardware: 0 DSP Multipliers (Pure Adders)
STAGE 4: BOUNDING BOX

Autonomous Tracker (Zero CPU Interrupts)

While software object trackers require OpenCV bounding-box algorithms that stall the CPU, this silicon architecture uses 4 concurrent hardware comparators running at 150 MHz.

Whenever the convolution engine flags an active edge pixel at coordinate (X, Y), the registers conditionally update: x_min = min(x_min, X), x_max = max(x_max, X), y_min = min(y_min, Y), and y_max = max(y_max, Y). At vertical sync (VSYNC), the bounding box is latched with zero CPU latency.

Tracking Latency: 0 Cycles (Instantly on VSYNC)
STAGE 5: LATENCY BUDGET

Pipeline Latency & Throughput Analysis

The total latency from the first camera pixel entering the chip to the first processed edge pixel leaving the chip is exactly 2 scanlines + 4 clock cycles (the time needed to fill both line buffers and propagate through the 3-stage adder tree).

Once the pipeline is primed, the hardware achieves a 100% duty cycle: exactly 1 processed pixel is produced on every single rising clock edge without pipeline bubbles, easily sustaining 1080p @ 60 FPS (124.8 MHz pixel clock) or 720p @ 120 FPS.

Sustained Throughput: 150 Mpixels / sec (1 Pixel/Cycle)
📄 SYNTHESIZABLE VERILOG RTL SOURCE CODE
sobel_core.v (Top Processing Pipeline)
line_buffer_fifo.v (Dual Row BRAMs)
window_3x3.v (Sliding Shift Registers)
bbox_tracker.v (Bounding Box Min/Max)

    

  


  
  

    

      
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Bit-Accurate RTL Emulation

        
Simulates exact fixed-point integer arithmetic and pipeline stages matching Cadence, Synopsys, and Vivado synthesis.

      

    

    

      
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Private Camera Stream

        
Webcam and video streams are processed 100% locally via Canvas WebGL buffers. No camera frames are stored or transmitted.

      

    

    

      
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FPGA & ASIC Ready

        
Verilog code is production-ready for Xilinx Vivado, Intel Quartus, and SkyWater 130nm OpenLane ASIC tapeouts.

      

    

  


  
  

    
Frequently Asked Questions


    

      
What is the latency of this hardware image processing pipeline?

      

        The latency is exactly 2 image lines + 4 clock cycles. The hardware must buffer the first 2 horizontal scanlines before the 3×3 matrix is valid. Once filled, it streams 1 processed pixel on every single rising clock edge without stalling.
      

    


    

      
Why does the Sobel operator require 0 DSP multipliers?

      

        The Sobel kernel contains coefficients [-1, 0, 1] and [-2, 0, 2]. Multiplying an 8-bit integer by 2 is accomplished in digital logic by shifting the bit vector left by 1 position (p << 1), which requires zero transistors. The entire convolution is implemented with a lightweight 3-stage adder tree.