Hands-on interactive simulators for RTL and VLSI concepts, plus reference guides for the EDA tools used in professional chip design. Every lab runs entirely in your browser — no installation, no account required.
Chip design is inherently visual and behavioral. A CDC synchronizer explanation makes more sense when you can watch what happens to the metastable flip-flop. An AXI handshake rule is easier to internalize when you can toggle VALID and READY yourself and see the transfer complete or stall. An LFSR scrambler clicks when you change the polynomial and watch the DC balance change in real time. EcrioniX's labs exist because reading theory is not enough — you need to build intuition for how the hardware actually behaves, and that intuition only develops through interaction. Each lab is paired with theory sections, RTL code, and interview-style questions, so you can connect the visual behavior back to the silicon reality.
The CDC lab shows a 2-FF synchronizer resolving metastability in real time, with a waveform that updates as you push data across domains. The AXI4 handshake lab shows VALID and READY as waveform signals, exactly as they appear in Verdi or DVT, so the protocol becomes muscle memory rather than memorized rules. The FSM lab lets you step through Moore and Mealy machines state by state and compare how their outputs differ in the waveform. These simulations run in the browser using JavaScript canvas and SVG — no Verilog simulator required for the visual intuition layer.
The EcrioniX Verilog simulator runs actual Icarus Verilog simulation server-side, returning real $display output and VCD waveform data. Unlike toy simulators, this supports full Verilog-2005 and much of SystemVerilog — always_ff, always_comb, logic types, interfaces, structs, and packed arrays. You can add a testbench, run it with Ctrl+Enter, see the console output, then flip to the waveform tab for a VCD viewer that supports zoom, scroll, and a live cursor readout. Click Synth to run Yosys synthesis and see a gate count and an interactive netlist diagram. It is the fastest way to verify a design concept without opening Vivado or DC Shell.
The EDA tool guides are not general-purpose tutorials. Git for VLSI explains tapeout branching strategy, partial checkout for large repositories, and tagging RTL snapshots at synthesis milestones. The Verdi guide explains how to debug CDC violations using the CDC analysis tab, how to set up the .rc file for consistent wave layouts across a team, and how to use the Tcl console for automating repetitive debug tasks. The SVN guide explains partial checkout for large repositories where the full PDK and GDS files cannot fit on a development machine — a VLSI-specific use case that generic SVN tutorials never mention.
Every lab on EcrioniX follows a consistent structure: the interactive simulation comes first (so you develop intuition), then the theory explains what you just observed (so you can reason about corner cases), then the RTL code shows the synthesis-correct implementation (so you can write it yourself). Each page ends with interview-style FAQ questions covering the tricky aspects — why the async FIFO pointer must be Gray-coded, why the clock mux uses falling-edge flip-flops, why the AXI master cannot de-assert VALID. These are exactly the questions asked in chip design interviews at companies like Intel, Qualcomm, Apple Silicon, and NVIDIA.
Browser-based simulations for hands-on understanding of VLSI and RTL design concepts.
Full ASIC IP project: upload any image, Python extracts RGB pixels, Verilog DUT converts to grayscale using integer hardware math, testbench verifies, Python reconstructs the output image.
Drag-and-drop logic gate simulator in the browser. Place AND, OR, NOT, NAND, NOR, XOR gates, connect wires, toggle input switches and watch signals propagate in real time. Loads with a NAND SR-latch demo.
Define registers with named bit-fields — width, offset, access (RW/RO/WO/W1C), reset — and export from one source: synthesizable Verilog (APB3 / AXI4-Lite + bridge), a UVM RAL model, IP-XACT XML, and a register datasheet PDF.
Edit two matrices and step a systolic array computing A×B cycle by cycle. Watch values flow through the MAC grid, accumulators build, and the result auto-verified against direct multiplication. The engine inside a TPU, made visible.
Watch parallel data get serialized onto one high-speed differential lane and deserialized back — animated step by step. Explore the TX/RX architecture (PISO, CDR, SIPO), 8b/10b encoding, and an interactive eye-diagram visualizer where you drag noise and watch the eye close.
Pilot a rocket booster to a soft, upright touchdown on the droneship. Throttle and gimbal with touch or keyboard while balancing five live parameters at once — descent rate, drift, tilt, spin and fuel — exactly like a real hoverslam. Can you stick the landing?
Race a CPU against a GPU and watch parallelism win in real time. Change the core count, then launch a SIMT kernel across many threads to see how one line of code runs on thousands of cores at once. Beginner-friendly and animated.
Configure cache size, block size and associativity, feed an address stream, and watch hits, misses, evictions, the tag/index/offset split and live hit-rate & AMAT animate. Direct-mapped, set-associative, fully associative with LRU/FIFO.
A timed game: an RTL snippet appears — find the bug before the clock runs out. Latch inference, blocking vs non-blocking, width mismatch, sensitivity lists & more. Score, rank & share. Plus a deep reference of the classic RTL bugs.
Drag gates and wire them to match the target truth table. Build XOR from NAND, a 2-of-3 majority voter, a 2:1 mux and more across 12 levels. Earn stars for beating par gate-count, then share your score.
Draw states and transitions on a canvas, mark the reset state, set conditions and outputs, then auto-generate synthesizable Verilog RTL. Moore or Mealy, with binary / one-hot / gray encoding. Live code, copy & download .v.
Full architecture of an AXI4-Lite → APB3 bridge: system block diagram, bridge FSM, write/read timing waveforms, port descriptions, and synthesizable Verilog RTL. The bridge behind the register map generator.
Complete architecture for a Request-Acknowledge CDC synchronizer. System diagram, 2-FF sync paths, 4-phase timing waveform, source & destination FSMs, full Verilog RTL, port spec, and when to use Req-Ack vs async FIFO.
Open-source ASIC IP for Sobel edge detection. Full architecture with 3×3 line buffers, sliding window, Gx/Gy kernel computation, and gradient magnitude pipeline. Complete theory, block diagrams, and port spec.
Fix 5 hands-on lint violation examples using real Verilator + iverilog checks. Covers implicit wires, width mismatches, incomplete sensitivity lists, undriven outputs, and blocking assignments in sequential blocks.
Paste Verilog RTL → Yosys SKY130 synthesis → OpenROAD initialize_floorplan. Returns die area, core area, utilisation % and row count on the SkyWater SKY130 HD PDK. Free, no install.
Complete reference for the OpenLane open-source physical design flow. Covers all stages: Yosys synthesis, OpenROAD floorplan/placement/CTS/routing, Magic DRC, Netgen LVS, and GDSII generation on the SkyWater SKY130 PDK.
Run static timing analysis on any Verilog design in the browser. Set clock frequency, synthesise to NanGate45 standard cells with Yosys, and get setup slack, WNS, TNS and critical path from OpenSTA.
Run Icarus Verilog simulation, view VCD waveforms, run Yosys synthesis, and get interactive gate-level netlist diagrams — all in the browser. Supports full Verilog-2005 and SystemVerilog. Share code with a permalink.
Click K-map cells to set minterms and don't-cares. The solver finds prime implicants and essential prime implicants, outputs the minimized SOP expression, and color-codes each group. Supports 2, 3, and 4 variables.
Interactive 2-FF synchronizer showing metastability resolution in real time. Push data across domains, vary clock frequencies, and watch the waveform to understand why the 2-clock settling window is required for safe synchronization.
Simulate an asynchronous FIFO with Gray code write/read pointers, 2-FF synchronizers, and FULL/EMPTY flag generation. Choose write and read frequencies, burst size, and FIFO depth to see how close the FIFO gets to overflow.
Watch AXI4 VALID/READY waveforms live for write and read channels. Toggle back-pressure to stall the slave and watch efficiency drop. See cycle-accurate transaction counts and a Verilog AXI4-Lite slave RTL implementation.
Simulate a 3-stage arithmetic pipeline with data hazard detection and stall insertion. Add instructions, watch data dependency hazards resolve through forwarding or stalls, and measure pipeline CPI (cycles per instruction).
Interactive Voltage Transfer Characteristic simulator. Adjust VDD, W/L ratio, Vtn, Vtp, channel-length modulation — watch VM, VIL, VIH, NML, NMH and the operating-point probe update live. Includes CMOS schematic and full theory.
Deep-dive theory + interactive waveform generator for all three essential serial protocols. Configure I²C address/data bytes, SPI CPOL/CPHA mode, UART frame format — see correct timing diagrams with bit labels, START/STOP, ACK, and sample markers. Interview-ready.
Step through a "101" sequence detector in both Moore and Mealy implementations simultaneously. See how Mealy fires one cycle earlier, and how the traffic light FSM shows that Moore outputs depend only on state. Verilog RTL included.
Compare round-robin vs fixed-priority arbitration with 4 simultaneous requestors. Enable all 4 requestors and watch how round-robin achieves Jain's Fairness Index of 1.00 while fixed priority starves lower-priority requestors.
XOR your bit stream with an LFSR (PCIe Gen3 polynomial or custom) and see the DC balance change. Change the polynomial, toggle bits, and verify the descrambled output matches the original. LFSR Verilog RTL included.
Toggle switches on pull-up, pull-down, and floating input circuits. Adjust resistor values and watch current, power, and voltage update in real time. Includes an I2C open-drain diagram showing why external pull-ups are mandatory for the Wired-AND property.
Interactive real-time eye diagram simulator. Tune data rate (1–10 Gbps), random jitter, channel loss (ISI), noise, and Tx pre-emphasis. Watch the eye open and close as you adjust each parameter. Measurements update live: eye height, eye width, Q factor, and estimated BER.
Four deep lab sessions: MOSFET I-V characteristics, CMOS inverter VTC with noise margins, subthreshold leakage (LVT/SVT/HVT), and transistor sizing trade-offs. Built for VLSI engineers who want to see the physics — not just the equations.
VLSI-focused guides for the version control and debug tools used in professional chip design flows — not generic tutorials.
Git commands and workflows tailored to chip design: tapeout branching strategies, tagging RTL snapshots at synthesis milestones, tracking SDC constraints and TCL scripts alongside RTL, and managing large binary files. Includes the complete daily workflow for RTL engineers.
Subversion workflows for large VLSI projects: partial checkout for repositories too large to clone in full, directory-level access control for foundry-confidential PDK files, atomic commits across interdependent RTL and constraint files, and branching strategy for tapeout milestones.
Perforce Helix Core commands and depot structure for semiconductor design. Covers changelists, pending vs submitted changes, workspaces, label management for release tagging, branching with Streams, and integration with Cadence and Synopsys tools.
Vim configuration and workflow for Verilog and SystemVerilog editing: syntax highlighting, RTL-specific key mappings, multi-file navigation with ctags for module hierarchy browsing, and macros for common RTL patterns like always_ff and module port declarations.
Synopsys Verdi waveform debugging for RTL and gate-level simulation: nTrace for hierarchical signal browsing, nSchema for RTL schematic view, CDC analysis integration, Tcl console for automating debug tasks, and .rc configuration for team-consistent wave layouts.
Traditional VLSI education relies on static textbook diagrams and end-of-chapter exercises that tell you what a circuit does without letting you observe it behaving incorrectly, recovering, or failing in a way that builds real intuition. An async FIFO with mismatched read/write frequencies and insufficient depth is just a diagram on paper — but push 12 writes at 250 MHz against a 125 MHz reader with a 4-entry FIFO and watch the FULL flag assert and data disappear, and the depth calculation formula suddenly carries meaning it cannot have from prose alone. Every interactive lab on EcrioniX is built around this principle: the simulation comes first, not last, so that when the theory section explains the mechanism, the reader is explaining something they already saw rather than memorizing something abstract.
Waveform literacy is a distinct skill from circuit design, and it is one that separates engineers who can debug gate-level simulation failures from those who cannot. The CDC lab shows the classic 2-FF synchronizer setup with variable clock ratios specifically because the failure mode — a metastable flip-flop whose output resolves to the wrong value — is invisible in RTL simulation unless the model is built to inject it. The Async FIFO lab generates the Gray-coded pointer values that must cross clock domains and shows the 2-FF synchronized copies lagging behind. Seeing these waveforms alongside the RTL makes the constraint clear: the pointer must be one-hot (Gray) at the crossing boundary because only then is a partial transition impossible. No single sentence in a textbook produces this understanding as reliably as watching the binary pointer produce corrupted full-flag decodes during a high-frequency burst.
At a chip design company, version control is not optional infrastructure — it is the backbone of every tapeout. When a synthesis run at block N completes, the RTL snapshot, the SDC constraint file, and the synthesis script are all committed together under a milestone tag so that if the PnR team reports a setup violation, the synthesis engineer can reproduce the exact run that produced the netlist. This pattern — tag at milestone, branch for tapeout, merge back to trunk — is specific to VLSI workflows and is not described in generic Git tutorials aimed at web developers. The Git for VLSI guide covers this branching model explicitly, along with how to use .gitattributes to handle binary SPICE and GDS files gracefully by marking them as binary so Git does not attempt to produce meaningless diffs of them. Similarly, the Perforce guide covers the Streams model used by large semiconductor companies where the PDK, the foundry deliverables, and the design RTL all live in separate streams with controlled integration between them — a structure that has no direct analogue in Git-based workflows.
The Verilog simulator is the most direct interface between a design and its behavioral proof. In a professional environment, the RTL designer writes a module and runs it through a regression of directed tests and constrained-random tests, but the first step — confirming that the module does what was intended — always involves a directed simulation with known inputs and expected outputs. The online compiler shortens this loop dramatically: rather than setting up an Icarus Verilog environment, creating a testbench file, compiling, running, and then invoking a VCD viewer like GTKWave, the entire sequence is a single browser action. The waveform viewer renders the VCD output inline. The Yosys synthesis view shows the RTL as a gate-level schematic, which is particularly useful for verifying that an always_comb block with incomplete case assignments has not accidentally inferred a latch — a structural check that the waveform alone does not expose. Together, the simulator, the waveform viewer, and the synthesis schematic provide a three-way verification that catches both behavioral and structural errors before a student or engineer invests time in full EDA tool setup.
Interview preparation for RTL and VLSI roles at companies like Qualcomm, Intel, Apple, NVIDIA, and Arm requires a specific depth of understanding that general embedded systems knowledge does not cover. The AXI4 handshake lab exists because a surprisingly large fraction of RTL design interviews include a question about the AXI VALID/READY protocol — specifically whether the master can de-assert VALID once asserted (it cannot), whether the slave can assert READY before VALID arrives (it can), and what the waveform looks like when back-pressure stalls a burst transfer. These are not facts to memorize; they are protocol behaviors to understand, and the lab makes the distinction visceral by letting the engineer toggle back-pressure and watch latency increase while throughput drops. The FSM lab similarly covers the Moore vs Mealy distinction — which is definitional in textbooks but becomes concrete only when you step through a "101" sequence detector in both implementations and observe that the Mealy output asserts one cycle before the Moore output. This cycle difference is often the source of interview follow-up questions about critical path timing and output stability, and seeing it in a live simulation makes the answer confident rather than rehearsed.