Claude for STA Engineers: AI-Assisted Static Timing Analysis

---
name: setup-timing-debugger
description: Diagnoses negative setup slack (max delay violations) across PVT corners, identifying root causes (deep logic cascades, detoured nets, high transition, clock skew deficits) and formulating precision closure actions.
---

# Setup Timing Debugger Skill

## Purpose
Systematically analyzes negative setup slack ($S_{\text{setup}} = T_{\text{required}} - T_{\text{arrival}} < 0$), determining whether the failure stems from architectural logic depth, weak cell drive strength, interconnect RC delay, clock network latency mismatch, or over-constrained SDC budgets.

## When to Activate
Activate when analyzing setup WNS/TNS regressions after synthesis, placement optimization, CTS, or detailed routing.

## Mathematical Formulation
$$\text{Data Arrival} = T_{\text{launch\_latency}} + T_{\text{CK}\to\text{Q}} + \sum T_{\text{cell}} + \sum T_{\text{net}}$$
$$\text{Data Required} = T_{\text{period}} + T_{\text{capture\_latency}} - T_{\text{setup}} - T_{\text{uncertainty}} + T_{\text{CPPR}}$$
$$\text{Slack}_{\text{setup}} = \text{Data Required} - \text{Data Arrival}$$

## Diagnostic Decision Tree
1. **Is Net Delay > 45% of Data Path Delay?**
   - *Yes:* Placement detour, high routing congestion, or unbuffered long net. Solution: Buffer insertion, layer promotion, or physical cell padding.
2. **Is Logic Depth > 20 levels for 1 GHz+ targets?**
   - *Yes:* Combinational logic cascade too deep. Solution: Architectural pipelining, register retiming, or logic restructuring.
3. **Are Input Transition Times > 120 ps on Critical Pins?**
   - *Yes:* Output driver starvation. Solution: Gate upsizing (e.g. `_X1` $\to$ `_X4`) or buffer insertion.
4. **Is Capture Clock Significantly Earlier than Launch Clock ($\Delta T_{\text{skew}} < -80\,\text{ps}$)?**
   - *Yes:* Clock tree imbalance. Solution: Useful skew scheduling or CTS trunk rebalancing.

## Limitations
- Setup fixes (upsizing, LVT swapping) increase dynamic and leakage power, and can create hold violations at fast/cold corners.

## Verification Checklist
- [ ] Setup slack verified under Slow-Slow-Global (SSG) corner at minimum $V_{DD}$.
- [ ] Proposed cell resizing evaluated against cell footprint compatibility.
- [ ] Downstream hold margin verified at Fast-Fast-Global (FFG) corner.

---
name: hold-timing-debugger
description: Diagnoses min-delay hold violations across fast/cold corners, evaluating short data paths, excessive positive clock skew, and prescribing safe delay buffer insertions that do not degrade setup slack.
---

# Hold Timing Debugger Skill

## Purpose
Investigates hold timing violations ($S_{\text{hold}} = T_{\text{arrival}} - T_{\text{required}} < 0$), ensuring data remains stable past the active capture clock edge to prevent race conditions and functional latch-up.

## Mathematical Formulation
$$\text{Data Arrival} = T_{\text{launch\_latency}} + T_{\text{CK}\to\text{Q}} + T_{\text{comb\_min}} + T_{\text{net\_min}}$$
$$\text{Data Required} = T_{\text{capture\_latency}} + T_{\text{hold}} + T_{\text{uncertainty}} - T_{\text{CPPR}}$$
$$\text{Slack}_{\text{hold}} = \text{Data Arrival} - \text{Data Required}$$

## Step-by-Step Analysis Workflow
1. **Corner Verification:** Confirm report is from Fast-Fast-Global (FFG) or Fast-Cold (0.85V, -40C / 125C) corner where silicon propagation is fastest.
2. **Data Path Inspection:** Measure logic depth. Many hold failures occur on shift registers, scan chains, or pipeline stages with 0 combinational gates between launch Q and capture D.
3. **Clock Skew Evaluation:** Check if capture clock latency exceeds launch clock latency ($\Delta T_{\text{skew}} = T_{\text{capture}} - T_{\text{launch}} > 0$). Excessive positive skew eats into the hold budget.
4. **Buffer Insertion Strategy:**
   - Select non-inverting delay buffers (`CLKBUF_X1`, `DELAY_X2`).
   - Place delay buffers physically close to the capture register D pin to minimize routing disruption.
   - Verify that adding delay does not turn a positive setup slack path negative at the slow corner.

## Limitations
- Adding excessive hold buffers increases standard cell density and dynamic switching power. Hold fixes must never be committed without multi-corner setup verification.

## Verification Checklist
- [ ] Hold analysis executed with on-chip variation derates and CPPR enabled.
- [ ] Setup slack margin confirmed $\ge T_{\text{inserted\_delay}} + 30\,\text{ps}$ at worst setup corner.
- [ ] Delay buffer footprint exists in standard cell target library.

---
name: sdc-constraint-reviewer
description: Audits Synopsys Design Constraints (SDC) for missing clocks, invalid false paths, erroneous multicycle hold multipliers, unconstrained ports, and conflicting clock groups.
---

# SDC Constraint Reviewer Skill

## Purpose
Performs rigorous syntactical and architectural audits of SDC/XDC constraint files, preventing under-constraining (which allows un-timed silicon failures) and over-constraining (which wastes routing resources and silicon area).

## Critical SDC Checks Performed
1. **Clock Definition Completeness:**
   - Verify all primary clock inputs have `create_clock` with explicit waveform `-waveform {0 period/2}`.
   - Audit PLL/divider outputs: Ensure `create_generated_clock` defines explicit `-source`, `-divide_by` or `-multiply_by`, and valid master clock pin.
2. **I/O Delay Constraints:**
   - Check all input ports have `set_input_delay -clock [get_clocks ...]` for both `-max` and `-min`.
   - Check all output ports have `set_output_delay -clock [get_clocks ...]` for both `-max` and `-min`.
   - Flag unconstrained I/O ports (`check_timing` unconstrained endpoints).
3. **Timing Exceptions Audit:**
   - `set_false_path`: Verify false paths are strictly applied to truly asynchronous or static control registers. Flag abuse of false paths used to mask real timing violations.
   - `set_multicycle_path`: Verify that whenever `set_multicycle_path N -setup` is declared, the corresponding `set_multicycle_path (N-1) -hold` is explicitly included.
   - `set_clock_groups`: Check `-asynchronous` groups between asynchronous domains; ensure synchronous sub-clocks are not accidentally severed.

## Limitations
- SDC review cannot verify board-level PCB trace propagation delays unless board design parameters are provided.

## Verification Checklist
- [ ] PrimeTime/Tempus `check_timing` run clean with zero unconstrained endpoints.
- [ ] Multicycle hold multipliers verified using waveform expansion.
- [ ] No false paths applied to clock pins or multi-bit CDC buses.

---
name: critical-path-analyzer
description: Pinpoints the most timing-critical paths in a design, clustering them by clock domain, logic cone, and physical hierarchy, and identifying structural bottlenecks across runs.
---

# Critical Path Analyzer Skill

## Purpose
Clusters and profiles the top 100+ violating paths from WNS down to zero slack, identifying whether timing violations are concentrated in a specific arithmetic datapath, state machine, register file, or interface module.

## Analysis Methodology
1. **Histogram & Distribution Profiling:**
   - Group violating endpoints by module hierarchy (e.g., `u_core/u_mmu`, `u_crypto/u_aes`).
   - Plot slack distribution: Determine whether violations are isolated (WNS anomaly) or systemic (widespread TNS wall).
2. **Common Sub-Cone Analysis:**
   - Trace backwards from violating D pins to find common gating logic, multiplexer trees, or shared ALU operands.
3. **QoR Scorecard Generation:**
   - Output WNS, TNS, Violating Endpoint Count (NVP), Worst Clock Domain, and Bottleneck Hierarchy.

## Limitations
- Cannot modify RTL source code directly; recommendations must be fed back to RTL designers or physical design engineers.

## Verification Checklist
- [ ] Critical paths verified across all active operating modes (functional, scan, BIST).
- [ ] Top bottleneck modules documented for architectural refactoring.

---
name: clock-skew-analyzer
description: Analyzes clock network latency, global skew, local skew, and useful skew scheduling between synchronous register pairs.
---

# Clock Skew Analyzer Skill

## Purpose
Evaluates post-CTS and post-route clock latency reports, distinguishing between harmless global skew across non-communicating blocks and dangerous local skew between synchronous launch-capture register pairs.

## Analysis Workflow
1. **Global Skew Evaluation:**
   - $\text{Global Skew} = \max(T_{\text{latency}}) - \min(T_{\text{latency}})$ across the entire clock tree.
   - Assess if tree balancing effort is within reasonable limits ($< 150\,\text{ps}$ for FinFET nodes).
2. **Local Skew Investigation:**
   - For communicating flip-flops: $\Delta T_{\text{local\_skew}} = T_{\text{capture\_latency}} - T_{\text{launch\_latency}}$.
   - Negative local skew ($T_{\text{capture}} < T_{\text{launch}}$) reduces available setup time.
   - Positive local skew ($T_{\text{capture}} > T_{\text{launch}}$) degrades hold margin.
3. **Useful Skew Verification:**
   - Audit whether EDA tool useful skew scheduling (e.g. Innovus CCOpt) has excessively delayed capture clocks, creating downstream hold traps.

## Limitations
- Clock latency values depend on extracted clock tree parasitic accuracy; pre-CTS estimations are purely speculative.

## Verification Checklist
- [ ] Local skew between critical communicating registers $< 40\,\text{ps}$.
- [ ] Clock buffers balanced symmetrically in technology library.

---
name: clock-tree-timing-reviewer
description: Reviews clock tree synthesis results, buffer depth, duty-cycle distortion, transition times on clock nets, and Integrated Clock Gating (ICG) enable timing.
---

# Clock Tree Timing Reviewer Skill

## Purpose
Reviews clock network topology reports, assessing buffer cascade depth, driver transition targets, clock duty cycle preservation, and ICG cell placement proximity to prevent setup violations on gating pins.

## Key Metrics Evaluated
1. **Buffer Depth & Level Balancing:**
   - Flag paths where clock buffer levels exceed 8–10 stages.
   - Check level mismatches between adjacent floorplan partitions.
2. **Clock Slew / Transition Times:**
   - Verify clock net transition times meet tight high-frequency limits ($T_{\text{trans}} \le 60\text{--}80\,\text{ps}$).
3. **Integrated Clock Gating (ICG) Timing:**
   - Audit setup and hold timing on ICG `E` (enable) pins.
   - Ensure ICG cells are placed close to sink registers to avoid clock latency divergence.

## Limitations
- Cannot alter clock routing topologies directly; requires feeding Tcl properties to CTS engines.

## Verification Checklist
- [ ] ICG enable setup slack $> 50\,\text{ps}$ across all corners.
- [ ] Clock buffer cells selected exclusively from symmetric balanced clock library variants.

---
name: mmmc-timing-analyzer
description: Coordinates Multi-Mode Multi-Corner (MMMC) timing analysis, mapping scenarios across process corners, voltages, temperatures, RC parasitics, and operational modes.
---

# MMMC Timing Analyzer Skill

## Purpose
Triages timing violations across high-dimensional MMMC scenario matrices, identifying whether violations are corner-specific (e.g., leakage-dominated high-temperature hold vs drive-starved low-voltage setup) or systemic across all modes.

## Multi-Corner Dimension Mapping
- **Process Corners:** Slow-Slow (SSG), Typical (TT), Fast-Fast (FFG), Global vs Local variation.
- **Voltage:** $V_{\text{nom}} \pm 10\%$ (e.g., $0.65\text{V}, 0.75\text{V}, 0.85\text{V}$).
- **Temperature:** $-40^\circ\text{C}$ (temperature inversion node check), $25^\circ\text{C}$, $125^\circ\text{C}$.
- **Extraction Corners:** Cbest (min capacitance), Cworst (max capacitance), RCbest, RCworst.
- **Operational Modes:** Functional Normal, High-Speed Turbo, Low-Power Sleep, Scan Shift, Scan Capture, At-Speed BIST.

## Diagnostic Workflow
1. Matrix generation: Tabulate WNS and TNS across all Mode $\times$ Corner pairs.
2. Isolate dominant corners: Identify which corner drives the worst setup slack and which drives worst hold.
3. Detect temperature inversion: Check if low temperature ($-40^\circ\text{C}$) yields worse setup slack than high temperature ($125^\circ\text{C}$) at advanced nodes ($< 16\,\text{nm}$).

## Limitations
- MMMC analysis requires extensive computational runs; Claude synthesizes and interprets existing scenario outputs.

## Verification Checklist
- [ ] Signoff scenario matrix covers all required foundry customer qualification corners.
- [ ] Temperature inversion verified at low Vdd corners.

---
name: ocv-aocv-pocv-reviewer
description: Audits On-Chip Variation (OCV), Advanced OCV (AOCV), and Parametric OCV (POCV / LVF) derating tables, timing graph depth, and common path pessimism removal (CPPR).
---

# OCV, AOCV & POCV Reviewer Skill

## Purpose
Audits statistical timing derates and on-chip variation configurations in PrimeTime and Tempus, verifying that margin models match foundry signoff guidelines without introducing excessive pessimism.

## Methodology Comparison
- **Traditional OCV:** Applies flat percentage derates (e.g., $+5\%$ late, $-5\%$ early) across the entire chip. Highly pessimistic on deep paths.
- **AOCV (Stage-Based):** Derates vary as a function of logic depth and physical path distance. Deeper logic paths receive lower derates due to statistical averaging.
- **POCV / LVF (Parametric / Liberty Variation Format):** Models delay variation as Gaussian distributions ($C \pm n\sigma$). Each cell delay includes nominal delay plus sensitivity coefficient ($\sigma$).

## Key Audit Checks
1. Verify `set_timing_derate` statements match foundry signoff runsets.
2. Confirm Clock Common Path Pessimism Removal (CPPR / CRPR) is enabled:
   `set_app_var timing_remove_clock_reconvergence_pessimism true`
3. Check POCV sigma threshold setting (typically $3\sigma$).

## Limitations
- Liberty Variation Format (LVF) tables are proprietary foundry IP; Claude analyzes derate commands and reports, not raw cell characterization tables.

## Verification Checklist
- [ ] CPPR enabled and validated in timing reports.
- [ ] POCV derate tables loaded and applied to both data and clock paths.

---
name: timing-violation-classifier
description: Categorizes thousands of timing violations into actionable buckets (logic depth, fanout, net detour, clock skew, constraint error, crosstalk) for systematic triage.
---

# Timing Violation Classifier Skill

## Purpose
Automates the classification of large-scale timing violation logs into discrete engineering categories, allowing team leads to assign specific paths to RTL designers, physical design engineers, or constraint owners.

## Classification Taxonomy
1. **Type A: Deep Logic Cascade** ($\text{Logic Levels} > 16$, Cell Delay $> 65\%$). Action: RTL designer logic restructuring or pipelining.
2. **Type B: Interconnect Detour** ($\text{Net Delay} > 45\%$). Action: Physical placement bound or buffer insertion.
3. **Type C: High Fanout Starvation** ($\text{Fanout} > 20$, Transition $> 120\,\text{ps}$). Action: Buffer tree synthesis.
4. **Type D: Clock Skew Deficit** ($T_{\text{skew}} < -100\,\text{ps}$). Action: CTS rebalancing.
5. **Type E: SDC Constraint Error** (Illegal I/O budget or false path omission). Action: SDC update.
6. **Type F: Crosstalk Delay Injection** ($\Delta T_{\text{SI}} > 80\,\text{ps}$). Action: Shielding or driver sizing.

## Expected Output
- Ranked breakdown table with violation count and percentage per category.
- Automated assignment recommendations.

## Limitations
- Rule-based heuristics require representative timing reports with net and transition reporting enabled.

## Verification Checklist
- [ ] All violating paths accounted for in categorization table.
- [ ] Root causes validated with sample path spot checks.

---
name: timing-eco-reviewer
description: Evaluates Engineering Change Order (ECO) scripts for timing closure, verifying cell sizing legality, buffer insertion site feasibility, and multi-corner side effect immunity.
---

# Timing ECO Reviewer Skill

## Purpose
Performs pre-commit audits of PrimeTime or Tempus ECO Tcl scripts (`size_cell`, `insert_buffer`, `swap_cell`), ensuring proposed fixes solve target violations without degrading hold timing, violating design rules (DRVs), or inducing routing congestion.

## Audit Workflow
1. **Footprint & Cell Legality:** Verify replacement cells share identical footprint and pinout with original instances.
2. **Setup vs Hold Trade-Off:** Verify that upsizing drivers or inserting LVT cells on setup-critical paths does not create hold violations at the fast corner.
3. **DRV Impact:** Ensure buffer insertions do not exceed max_capacitance or max_transition limits on driving nets.
4. **Physical Density:** Verify ECO buffers are placed into legal placement sites with adequate local whitespace.

## Example Output
```text
ECO Audit Summary:
  Total Commands: 42 (28 size_cell, 14 insert_buffer)
  Setup Improvement Expected: +85 ps WNS
  Hold Risk Detected: 2 paths near threshold (Paths #12, #29)
  Recommendation: Add hold delay buffer on Path #12 capture pin before commit.
```

## Limitations
- Claude cannot guarantee physical routability of inserted ECO buffers; incremental PnR execution is mandatory.

## Verification Checklist
- [ ] Replacement cells verified in target technology library.
- [ ] Incremental STA run clean across all MMMC signoff corners.
- [ ] Formal equivalence (LEC) verified post-ECO.

---
name: timing-report-comparator
description: Compares two timing reports (pre-ECO vs post-ECO, or Run A vs Run B), isolating regressions, fixed paths, and net WNS/TNS changes.
---

# Timing Report Comparator Skill

## Purpose
Performs side-by-side delta analysis between two timing report runs, flagging which paths improved, which regressed, and calculating exact WNS/TNS shifts across implementation milestones.

## Metric Deltas Computed
- $\Delta\text{WNS} = \text{WNS}_{\text{Run B}} - \text{WNS}_{\text{Run A}}$
- $\Delta\text{TNS} = \text{TNS}_{\text{Run B}} - \text{TNS}_{\text{Run A}}$
- $\Delta\text{NVP} = \text{Violating Count}_{\text{Run B}} - \text{Violating Count}_{\text{Run A}}$
- Endpoint-by-endpoint correlation: Identifies newly violating endpoints that were previously meeting timing.

## Limitations
- Requires both reports to be generated under identical SDC constraints and operating corners to prevent false regression flags.

## Verification Checklist
- [ ] Consistent corner comparison verified.
- [ ] Zero un-tracked regressions introduced.

---
name: sta-tcl-automation
description: Generates, debugs, and refines custom Tcl scripts for Synopsys PrimeTime and Cadence Tempus, automating path extraction, violation reporting, and custom check loops.
---

# STA Tcl Automation Skill

## Purpose
Writes clean, modular, and robust Tcl automation procedures for PrimeTime (`pt_shell`) and Tempus, extracting timing attributes, formatting custom CSV summaries, and creating batch analysis pipelines.

## Capabilities
- Custom collection filtering (`get_timing_paths`, `get_cells`, `get_nets`).
- Iterating through path collections to extract startpoint, endpoint, slack, and delay components.
- Automating CSV and markdown table generation directly from EDA shells.

## Limitations
- Tcl syntax must strictly match target tool shell versions. Claude avoids deprecated or proprietary unverified commands.

## Verification Checklist
- [ ] Tcl procedure syntax checked with clean source execution in `pt_shell` or `tempus`.
- [ ] Memory-efficient collection handling implemented (e.g. freeing large collections).

---
name: timing-regression-analyzer
description: Investigates unexpected timing regressions between physical implementation stages (e.g. Post-CTS to Post-Route), tracing degradation to routing parasitics, clock latency shifts, or cell displacement.
---

# Timing Regression Analyzer Skill

## Purpose
Diagnoses why timing closed at an earlier stage (e.g., post-placement or post-CTS) degrades severely after subsequent flow steps (e.g., detailed routing or SPEF signoff extraction).

## Diagnostic Investigation
1. **Parasitic Modeling Shift:** Compare wireload models vs virtual route vs extracted 3D SPEF.
2. **Clock Tree Latency Shift:** Compare ideal clock vs propagated clock network insertion delays.
3. **Crosstalk Delay Injection:** Compare timing slack with SI disabled vs SI enabled.
4. **Physical Displacement:** Check if detailed legalizer or detailed router moved critical path cells.

## Limitations
- Cannot reconstruct physical geometry without DEF and SPEF database inspection in the EDA environment.

## Verification Checklist
- [ ] Parasitic extraction settings matched to signoff specs.
- [ ] Propagated clock timing validated post-CTS.

---
name: si-crosstalk-timing-reviewer
description: Analyzes Signal Integrity (SI) crosstalk delay and glitch reports, identifying victim-aggressor coupling nets, Miller effect delay shifts, and recommending physical shielding or driver resizing.
---

# SI Crosstalk Timing Reviewer Skill

## Purpose
Inspects PrimeTime SI or Tempus SI crosstalk analysis outputs, evaluating how dynamic switching on aggressor nets impacts victim net propagation delay (Miller effect) and functional voltage glitch noise.

## Physics Evaluated
- **Crosstalk Setup Delay:** Aggressor switching in opposite direction increases effective coupling capacitance ($C_{\text{eff}} \approx 2 \cdot C_c$), expanding transition time and causing setup violations.
- **Crosstalk Hold Delay:** Aggressor switching in same direction accelerates victim transition ($C_{\text{eff}} \approx 0$), speeding up arrival time and inducing hold violations.
- **Glitch Noise Margin:** Static net experiences voltage bounce due to capacitive charge injection. Peak glitch must remain below library $V_{\text{noise\_margin}}$.

## Prescribed Physical Fixes
1. Upsize victim driver to lower driving impedance.
2. Downsize aggressor driver if aggressor path has excess slack.
3. Insert repeater buffer on long victim interconnect.
4. Shield victim net with VDD/VSS tracks or increase routing track spacing.

## Limitations
- SI calculation requires accurate coupled parasitic extraction (`*C_COUP` in SPEF); lumped capacitance is completely inadequate for SI signoff.

## Verification Checklist
- [ ] Extracted SPEF contains explicit cross-coupling capacitors.
- [ ] Peak glitch height $< 25\%$ of supply voltage ($V_{DD}$).