Claude for RTL Design Engineers: Practical AI-Assisted ASIC Design

---
name: systemverilog-lint-review
description: Analyzes EDA static lint violation reports (SpyGlass, Veridian, Synopsys, Cadence HAL) and provides root-cause diagnosis and non-breaking RTL fixes.
---

# SystemVerilog Lint Review Skill

## Purpose
Interprets industrial static lint violation logs from commercial EDA tools (Synopsys SpyGlass, Siemens Questa Lint, Cadence HAL, Verilator) and provides actionable root-cause analysis and minimal-impact RTL repairs.

## When to Activate
Activate when an engineer pastes lint warnings/errors or requests automated resolution of lint rule violations.

## Required Inputs
- Lint report log snippet (Rule ID, message, file, line number)
- Associated SystemVerilog RTL module source code
- Target tool name / rule set (e.g., SpyGlass Lint, STARC, OpenMORE)

## Step-by-Step Workflow
1. **Rule Classification:** Parse Rule IDs (e.g., `W415a` latch inference, `W164b` truncation, `W240` unused net, `W188` signedness mismatch).
2. **Context Correlation:** Pinpoint exact source lines and identify the underlying hardware construct triggering the warning.
3. **False Positive vs True Defect Assessment:**
   - Determine whether the rule violation represents a true functional hazard (e.g., unintentional vector drop) or an intentional design choice (e.g., unused upper bits of a counter).
4. **Remediation Strategy:**
   - True Defect: Formulate an exact RTL correction maintaining functional equivalence.
   - False Positive / Intentional: Provide tool waiver syntax (e.g., `// spyglass disable_block W240`) or standard SV lint-clean coding idiom.
5. **Impact Verification:** Confirm the suggested modification introduces zero simulation divergence or timing impact.

## Technical Constraints
- Never mask a genuine functional defect with a tool waiver comment without explicit engineer confirmation.
- Ensure all bit slices remain explicitly dimensioned.

## Output Format
- **Violation Breakdown Table:** Rule ID | Severity | Root Cause | Fix Strategy
- **Corrected Code Snippets:** Before vs After with exact diff.
- **Recommended Waiver Directives:** If applicable, formatted for SpyGlass / Verilator.

## Validation Checklist
- [ ] Root cause verified against IEEE 1800-2023 semantics.
- [ ] Fix does not modify module latency or pinout.
- [ ] No unintended latch or multi-driver introduced by the fix.

## Example Invocation
```text
/systemverilog-lint-review
Tool: SpyGlass 2023.09
Violations:
- W164b: Truncation in assignment: rhs width 32, lhs width 16 (fifo_ctrl.sv:84)
- W415a: Latch inferred for signal 'next_state' (fsm.sv:52)
```

---
name: fifo-design-review
description: Evaluates synchronous and asynchronous FIFO architectures for Gray-code pointer safety, almost-full/empty calculation, overflow protection, and CDC integrity.
---

# FIFO Design Review Skill

## Purpose
Audits dual-clock and single-clock FIFO implementations for pointer math correctness, empty/full detection, almost-empty/almost-full watermarks, circular memory wrap-around, and CDC safety.

## When to Activate
Activate when designing, verifying, or debugging FIFO buffers, queue controllers, or latency bridges.

## Required Inputs
- FIFO SystemVerilog source code
- Clock domain specifications (Synchronous single-clock vs Asynchronous dual-clock)
- Depth and Data Width parameters
- Watermark requirements (programmable empty/full threshold levels)

## Step-by-Step Workflow
1. **Pointer Dimensioning:** Confirm pointer width is $N+1$ where Depth = $2^N$ to distinguish full from empty.
2. **Gray Code Conversion Audit (Async FIFO):**
   - Verify binary-to-Gray conversion: `assign gray_ptr = bin_ptr ^ (bin_ptr >> 1)`.
   - Verify Gray-to-binary conversion logic in the destination domain.
   - Confirm Gray pointers are registered before crossing clock boundaries.
3. **Synchronizer Chain Verification:**
   - Confirm 2-stage (or 3-stage) flip-flop synchronizers exist on pointer crossings.
   - Check for `(* ASYNC_REG = "TRUE" *)`, `set_false_path`, or `set_max_delay -datapath_only` constraint requirements.
4. **Full and Empty Flag Generation:**
   - Empty: `assign empty = (rptr_gray == wptr_gray_sync)` in read domain.
   - Full: Verify top two MSBs inverted with lower bits identical: `assign full = (wptr_gray == {~rptr_gray_sync[N:N-1], rptr_gray_sync[N-2:0]})`.
5. **Simultaneous Push/Pop Hazards:** Check behavior when `wr_en` and `rd_en` assert concurrently under edge conditions.
6. **Watermark / Level Counter Accuracy:** Audit almost-full and almost-empty calculations for one-cycle latency offset.

## Technical Constraints
- Non-power-of-2 depth asynchronous FIFOs require specialized Gray coding or dual-pointer math; flag non-$2^N$ depth as a critical CDC risk.

## Output Format
- **Architecture Assessment:** Synchronous vs Asynchronous assessment.
- **Pointer & Synchronizer Audit:** Detailed analysis of pointer generation and CDC path.
- **Flag Correctness Review:** Mathematical verification of empty/full formulas.
- **SVA Assertions:** SystemVerilog assertions to prove safety.

## Validation Checklist
- [ ] Pointer width is $\log_2(	ext{DEPTH}) + 1$.
- [ ] Gray code changes by only 1 bit per increment.
- [ ] Full condition verified in write clock domain.
- [ ] Empty condition verified in read clock domain.
- [ ] Write into full and read from empty are strictly prevented.

## Example Invocation
```text
/fifo-design-review
Review this async FIFO for a 16-deep 64-bit PCIe-to-AXI bridge:
[paste async_fifo.sv]
```

---
name: cdc-rdc-review
description: Analyzes clock-domain crossings (CDC) and reset-domain crossings (RDC) for metastability hazards, reconvergence, bus skew, and reset deassertion safety.
---

# Clock & Reset Domain Crossing (CDC/RDC) Review Skill

## Purpose
Identifies asynchronous timing hazards, metastability risks, multi-bit coherency bugs, reconvergence artifacts, and reset assertion/deassertion vulnerabilities in multi-clock ASIC SoCs.

## When to Activate
Activate when analyzing multi-clock RTL, async reset distribution, or preparing for Questa CDC / Synopsys VC CDC signoff.

## Required Inputs
- Multi-clock SystemVerilog RTL modules
- Clock definition list (clock frequencies, domains, asynchronous relationships)
- Reset architecture (asynchronous assert / synchronous deassert scheme)

## Step-by-Step Workflow
1. **Clock Domain Identification:** Map every flip-flop to its originating clock tree.
2. **Single-Bit Crossing Audit:**
   - Ensure multi-flop synchronizers (2-FF / 3-FF) are deployed on all async control signals.
   - Verify pulse synchronizers (toggle-type) for fast-to-slow clock domain pulses.
3. **Multi-Bit Crossing Audit (Crucial):**
   - Check for unsafe multi-bit CDC: Flag any instance where individual bits of a binary bus cross through separate synchronizers.
   - Mandate Gray code conversion, asynchronous FIFO, or Valid/Ready 4-phase handshake synchronizer.
4. **Reconvergence Analysis:**
   - Detect signals that cross asynchronously, synchronize separately, and subsequently converge into common combinational logic.
5. **Reset Domain Crossing (RDC):**
   - Check that asynchronous resets use an Asynchronous Assert, Synchronous Deassert (AASD) synchronizer per clock domain.
   - Check for reset race conditions on sequential circuits during power-up/wake-up.

## Technical Constraints
- Never declare a CDC path "clean" based solely on simulation or code inspection. State clearly that Questa CDC / VC CDC / SpyGlass CDC and SDC constraints (`set_clock_groups -asynchronous`) are mandatory for sign-off.

## Output Format
- **Domain Topology Table:** Clock A -> Clock B | Signal Name | Synchronizer Topology | Hazard Status
- **Identified Hazards & Risks:** Explanation of potential failure modes (metastability, skew, reconvergence).
- **Hardened SystemVerilog Module:** Safe synchronizer implementation.
- **Synthesis/STA Directives:** Necessary false-path / max-delay constraints.

## Validation Checklist
- [ ] All async signals pass through dedicated synchronizers.
- [ ] No binary counters cross domains without Gray coding or handshaking.
- [ ] Reset release synchronized to destination clock edge.
- [ ] Synchronizer flip-flops marked with `DONT_TOUCH` and `ASYNC_REG`.

## Example Invocation
```text
/cdc-rdc-review
Review this clock-crossing block between 400MHz AXI and 100MHz APB:
[paste cdc_bridge.sv]
```

---
name: apb-axi-protocol-review
description: Verifies APB4, AXI4-Lite, and AXI4 ready/valid handshake protocols, backpressure, burst rules, outstanding transactions, and skid buffers.
---

# APB & AXI Protocol Review Skill

## Purpose
Audits AMBA APB4, AXI4-Lite, and AXI4 bus interfaces for protocol compliance, deadlock freedom, zero-bubble throughput, skid buffer integration, and backpressure correctness.

## When to Activate
Activate when writing or inspecting memory-mapped bus interfaces, peripherals, crossbars, DMA controllers, or protocol converters.

## Required Inputs
- Protocol type (AMBA APB4, AXI4-Lite, AXI4 Full)
- Role (Master / Subordinate / Interconnect)
- SystemVerilog RTL source code
- Outstanding transaction / burst capability specifications

## Step-by-Step Workflow
1. **Handshake Rule Verification (AXI/AXI-Lite):**
   - Verify ARM AXI Rule: `VALID` signal must NEVER depend combinationally on `READY` (prevents deadlock).
   - Verify `READY` may depend on `VALID`.
   - Verify once `VALID` is asserted, payload and `VALID` remain asserted until `READY` is high (Handshake Stability Rule).
2. **APB4 Protocol Compliance:**
   - Verify two-cycle access: Setup phase (`PSEL=1, PENABLE=0`) followed by Access phase (`PSEL=1, PENABLE=1`).
   - Audit `PREADY` wait-state handling and `PSLVERR` error response.
   - Verify write strobe (`PSTRB`) and byte-lane routing.
3. **Skid Buffer & Throughput Audit:**
   - If registered `READY` output is required to break long combinational timing paths, ensure a 2-stage skid buffer is used to prevent throughput drops.
4. **Channel Decoupling (AXI):**
   - Confirm Write Address (AW), Write Data (W), Write Response (B), Read Address (AR), and Read Data (R) channels function independently.
5. **Reset & Flush Integrity:**
   - Ensure `ARVALID`, `AWVALID`, `WVALID`, `BVALID`, and `RVALID` deassert to 0 on reset.

## Technical Constraints
- Strict adherence to official ARM AMBA AXI and APB protocol specifications (IHI0022E / IHI0024C).

## Output Format
- **Protocol Compliance Matrix:** Check results for all core AMBA rules.
- **Timing & Handshake Diagrams:** ASCII or WaveDrom sequence of legal/illegal transfers.
- **Identified Bugs & Corner Cases:** Deadlocks, dropped beats, unstable payloads.
- **Compliant RTL Fix:** Corrected module code.

## Validation Checklist
- [ ] No `VALID` waiting on `READY` combinationally.
- [ ] Data holds stable until handshake completes.
- [ ] Skid buffer implemented if `READY` is registered.
- [ ] `PREADY` and `PSLVERR` legal in APB Access phase.

## Example Invocation
```text
/apb-axi-protocol-review
Protocol: AXI4-Lite Subordinate
Check if this register slice violates the AXI handshake rules:
[paste axi_reg_slice.sv]
```

---
name: synthesis-report-analysis
description: Interprets Cadence Genus and Synopsys Design Compiler synthesis reports (QoR, area, gate count, cell distribution) and guides RTL optimization.
---

# Synthesis Report Analysis Skill

## Purpose
Diagnoses post-synthesis QoR (Quality of Results) reports from Synopsys Design Compiler (`dc_shell`) and Cadence Genus Synthesis Solution, mapping gate-level bottlenecks back to RTL microarchitecture.

## When to Activate
Activate when analyzing synthesis logs, area breakdowns, high-gate-count modules, or cell utilization reports.

## Required Inputs
- Synthesis report text (e.g., `report_qor`, `report_area -hierarchy`, `report_gates`)
- Tool identity (Synopsys DC vs Cadence Genus)
- Target technology node and cell library (e.g., TSMC N5, GF 22FDX, SkyWater 130)
- Associated SystemVerilog RTL source code

## Step-by-Step Workflow
1. **Metrics Extraction:**
   - Extract Total Cell Area, Sequential Area, Inverter/Buffer Area, Combinational Area.
   - Check macro count (RAMs, ROMs, PLLs) vs standard cell logic.
2. **Sequential vs Combinational Ratio Analysis:**
   - Identify abnormally high flop-to-combinational ratios (potential over-pipelining or bloated register files).
   - Identify excessive combinational logic per flop (insufficient pipelining).
3. **Logic Structure Diagnosis:**
   - Detect bloated arithmetic units: Look for multi-bit dividers, unshared multipliers, or 64-bit adders mapped to generic ripple-carry logic.
   - Detect huge multiplexer trees: Large case statements or dynamic bus multiplexers causing area explosion.
4. **Cell Type Breakdown:**
   - Identify excessive inverter/buffer count indicating severe fanout or long design rules.
   - Check high-drive cell utilization (potential dynamic power and area penalty).
5. **Formulate RTL Microarchitecture Action Plan:**
   - Provide concrete RTL refactoring strategies (operator sharing, state encoding, mux restructuring).

## Technical Constraints
- Never modify functional behavior when recommending area-reduction transformations.
- Acknowledge difference between wireload-model synthesis and physical synthesis (e.g., DC-Topo / Genus iSpatial).

## Output Format
- **Synthesis Summary Scorecard:** Area, Instances, Flop Count, Combinational Depth.
- **Hotspot Hierarchy Table:** Modules ranked by area contribution percentage.
- **Root-Cause RTL Assessment:** Specific lines of code causing cell bloat.
- **Actionable Optimization Recommendations:** Code diffs for resource sharing and mux pruning.

## Validation Checklist
- [ ] Area numbers properly categorized by standard cell vs macro.
- [ ] RTL modifications preserve clock-cycle latency and protocol contracts.
- [ ] Synthesis constraints (operating condition, wireload model) accounted for.

## Example Invocation
```text
/synthesis-report-analysis
Tool: Synopsys Design Compiler 2022.12
Report: [paste report_area.rpt]
RTL: [paste crypto_engine.sv]
```

---
name: timing-report-analysis
description: Analyzes setup and hold static timing analysis (STA) path reports from Synopsys PrimeTime, Design Compiler, or Cadence Genus/Tempus to guide RTL path remediation.
---

# Timing Report Analysis Skill

## Purpose
Decodes complex Static Timing Analysis (STA) critical path reports, isolates data-arrival bottlenecks, and formulates RTL-level architectural timing closure strategies.

## When to Activate
Activate when an engineer has negative slack (WNS/TNS) in setup (`max_delay`) or hold (`min_delay`) paths post-synthesis or post-place-and-route.

## Required Inputs
- STA Timing Report snippet (`report_timing -nosplit -transition_time -nets -attributes`)
- Clock period and operating corner (e.g., SSG 0.675V -40C, TT 0.8V 25C)
- RTL module source code corresponding to the failing timing path

## Step-by-Step Workflow
1. **Slack & Constraint Extraction:**
   - Identify WNS (Worst Negative Slack), clock period, required time, arrival time, clock uncertainty.
2. **Path Topology Deconstruction:**
   - Trace Startpoint (launch flip-flop `CK -> Q`), Combinational Path, and Endpoint (capture flip-flop `D`).
   - Check clock skew between launch clock path and capture clock path.
3. **Delay Component Breakdown:**
   - Calculate Cell Delay vs Net (Interconnect) Delay percentage.
   - Count logic depth (number of gates between launch and capture).
   - Identify High Fanout Nets (HFN) on the datapath.
4. **Identify RTL Timing Antipatterns:**
   - Cascaded priority encoders (`if-else` chains on wide buses).
   - Deep arithmetic operations (e.g., adder followed by comparator followed by shifter in single cycle).
   - Wide multi-bit multiplexers before register input.
5. **Remediation Strategy Formulation:**
   - Recommend targeted RTL transformations: Pipelining (register retiming), Shannon decomposition, parallel prefix restructuring, or pre-decoding control signals.

## Technical Constraints
- Never change cycle latency without architectural permission. If a pipeline stage cannot be added, focus on logic flattening and balancing.

## Output Format
- **Path Breakdown Table:** Stage | Cell Type | Fanout | Cell Delay | Net Delay | Cumulative
- **Bottleneck Diagnosis:** Pinpoint the exact RTL expression consuming excessive delay.
- **RTL Refactoring Solution:** Code replacement with flattened logic or balanced multiplexing.
- **Downstream Tool Recommendations:** Directives for synthesis (e.g., grouping, path priority).

## Validation Checklist
- [ ] Logic depth verified against clock period budget (rule of thumb: ~25-30 FO4 per ns).
- [ ] Clock skew identified as either helping or hurting slack.
- [ ] Solution does not break cycle-by-cycle interface contracts.

## Example Invocation
```text
/timing-report-analysis
Clock Period: 1.0 ns (1 GHz target)
Slack: -240 ps WNS
Report: [paste report_timing.rpt]
RTL: [paste packet_parser.sv]
```

---
name: sva-generator
description: Generates formal SystemVerilog Assertions (SVA) for protocols, FIFOs, FSMs, arbiters, and interface contracts with assume/assert/cover properties.
---

# SystemVerilog Assertions (SVA) Generator Skill

## Purpose
Synthesizes high-coverage, mathematically precise SystemVerilog Assertions (SVA) for simulation monitoring and formal property verification (FPV) in Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal.

## When to Activate
Activate when verifying protocols, creating formal testbenches, adding interface assertions, or proving safety and liveness properties.

## Required Inputs
- Design specification or SystemVerilog RTL module
- Target interface signals (Clock, Reset, Control, Data)
- Property requirements (e.g., no overflow, mutual exclusion, handshake stability, starvation freedom)
- Verification mode (Dynamic Simulation vs Formal Property Verification)

## Step-by-Step Workflow
1. **Clock & Reset Setup:** Define default clocking block and disable condition:
   ```systemverilog
   default clocking cb @(posedge clk); endclocking
   default disable iff (!rst_n);
   ```
2. **Immediate vs Concurrent Classification:**
   - Use concurrent assertions (`property ... endproperty`) for temporal relationships.
   - Use immediate assertions for one-shot sanity checks in combinational logic.
3. **Safety Properties (Bad things never happen):**
   - Write/Read bounds (FIFO never writes when full, never reads when empty).
   - Mutual exclusion (one-hot state encoding, grant arbiter outputs).
   - Protocol invariants (AXI `VALID` stable until `READY`, `ADDR` aligned).
4. **Liveness Properties (Good things eventually happen):**
   - Eventual response under fairness assumptions: `req |-> s_eventually ack`.
5. **Assume vs Assert Partitioning:**
   - Tag module inputs with `assume property` (environment constraints).
   - Tag module internal states and outputs with `assert property` (design proof).
   - Add `cover property` for reachability verification.

## Technical Constraints
- Distinguish overlapping implication (`|->`) from non-overlapping implication (`|=>`).
- Avoid unbounded liveness assertions in simulation that cause performance collapse.

## Output Format
- **Assertion Specification Table:** Property Name | Type (Safety/Liveness) | Intent | Formal Rule
- **Self-Contained SVA Checker Module:** Ready to bind via `bind` construct.
- **Formal Verification Command Script:** Basic setup for JasperGold or VC Formal.

## Validation Checklist
- [ ] All properties use appropriate `disable iff (!rst_n)`.
- [ ] Implication operators properly selected (`|->` vs `|=>`).
- [ ] No race conditions between assertion evaluation and NBA updates.
- [ ] SVA module cleanly bindable without modifying original RTL source.

## Example Invocation
```text
/sva-generator
Generate comprehensive SVA assertions for an AXI4-Lite Slave interface:
Clock: clk, Reset: rst_n
Signals: awvalid, awready, wvalid, wready, bvalid, bready, bresp
```

---
name: low-power-upf-review
description: Audits low-power RTL constructs, Integrated Clock Gating (ICG), power domain isolation, retention flip-flops, and IEEE 1801 UPF compatibility.
---

# Low-Power RTL & UPF Review Skill

## Purpose
Examines RTL designs for power optimization compatibility, Integrated Clock Gating (ICG) enablement, power domain partitioning, retention strategies, and IEEE 1801 UPF (Unified Power Format) consistency.

## When to Activate
Activate when auditing battery-powered, mobile, or high-efficiency ASIC subsystems with multi-voltage domains or power-gated blocks.

## Required Inputs
- SystemVerilog RTL modules
- Power architecture intent (Power Switch, Isolation, Level Shifter, State Retention)
- UPF / CPF specification (optional)
- Clock gating targets and minimum enable bit-widths

## Step-by-Step Workflow
1. **Clock Gating Efficiency Audit:**
   - Detect data-recirculating registers lacking enable signals: `if (load_en) q <= d; else q <= q;`.
   - Ensure enable signals have sufficient idle periods to justify ICG cell insertion.
   - Flag clock gating on registers narrower than minimum threshold (typically 4 or 8 bits).
2. **Power Gating Sequence Review:**
   - Audit Power Management Controller FSM:
     1. Assert isolate enable (`iso_en = 1`).
     2. Assert reset (`rst_n = 0`).
     3. Deassert power switch (`pwr_sw = 0`).
     4. Power-up reverse order: Power switch on -> stabilize -> deassert reset -> release isolation.
3. **Isolation Cell Readiness in RTL:**
   - Ensure signals leaving a power-down domain connect to well-defined clamping values (0, 1, or latch) during sleep.
   - Never implement isolation logic with standard gates in RTL if UPF will insert library ISO cells (avoids double-isolation).
4. **Level Shifter Awareness:**
   - Audit cross-domain nets between different $V_{DD}$ rails.
5. **Memory Power States:**
   - Review SRAM sleep, deep-sleep, and shutdown pins.

## Technical Constraints
- Never mix UPF intent with structural RTL isolation gates; clearly distinguish RTL functional requirements from UPF synthesis-inserted physical cells.

## Output Format
- **Power Optimization Audit Table:** Optimization Opportunity | Domain | Estimated Savings | Risk
- **Clock Gating Clean RTL:** Refactored register descriptions.
- **Power Sequencing FSM Review:** Analysis of wake-up/sleep state machines.
- **Companion UPF Snippet:** Matching IEEE 1801 `set_isolation`, `create_power_domain` directives.

## Validation Checklist
- [ ] Clock enables are glitch-free and ICG-cell synthesizable.
- [ ] Isolation signals clamped correctly prior to power switch disable.
- [ ] Retention registers properly controlled.
- [ ] No floating inputs during sleep states.

## Example Invocation
```text
/low-power-upf-review
Review this power domain controller FSM and isolated output interfaces:
[paste pwr_ctrl.sv]
```

---
name: rtl-specification-to-design
description: Converts architectural English specifications into synthesizable SystemVerilog RTL with cycle-by-cycle execution tables, datapath registers, and FSMs.
---

# RTL Specification-to-Design Skill

## Purpose
Translates natural-language microarchitecture documents, interface tables, and functional specifications into verified, synthesizable SystemVerilog RTL with strict hardware discipline.

## When to Activate
Activate when initiating a new hardware block, implementing an accelerator datapath, or translating an architectural micro-spec into RTL.

## Required Inputs
- Functional requirement or microarchitecture description
- Interface definitions (Ports, Widths, Protocols: AXI, APB, Ready/Valid, Streaming)
- Clocking, reset, and performance targets (e.g., single-cycle throughput, latency)
- Parameterization requirements (Data widths, buffer depths)

## Step-by-Step Workflow
1. **Specification Gap Analysis:**
   - Interrogate the prompt for missing hardware constraints: Backpressure behavior, reset state, simultaneous transactions, error handling.
2. **Cycle-by-Cycle Execution Table:**
   - Construct a timing table showing signals for typical, edge-case, and backpressured clock cycles.
3. **Partitioning Datapath vs Control:**
   - Isolate control paths (FSMs, counters, handshake arbiters) from datapaths (ALUs, multiplexers, registers).
4. **SystemVerilog Implementation:**
   - Use clean IEEE 1800-2023 constructs: `always_ff`, `always_comb`, parameterized widths, typed enumerations.
5. **Self-Review for Synthesizability:**
   - Ensure zero latches, no multi-driver nets, and complete sensitivity.

## Technical Constraints
- Never invent interface signals not implied by the architecture.
- Always include explicit reset values for all registers.

## Output Format
- **Microarchitecture Summary:** Datapath block diagram description and pipeline stages.
- **Cycle Timing Matrix:** Step-by-step cycle execution table.
- **Complete Synthesizable SystemVerilog RTL:** Ready for compilation.
- **Design Assumptions & Unspecified Corner Cases:** Explicit list of decisions made.

## Validation Checklist
- [ ] All inputs registered or combinationally processed cleanly.
- [ ] Handshakes obey standard ready/valid rules.
- [ ] Full parameterization with safe default values.
- [ ] Lint-clean and synthesizable in Synopsys DC and Cadence Genus.

## Example Invocation
```text
/rtl-specification-to-design
Design a Credit-Based Flow Control Receiver:
- In: 32-bit data + valid
- Out: 8-bit credit return pulse
- Internal 8-entry buffer
- Clock: 250MHz, sync reset active-high
```

---
name: rtl-regression-debugger
description: Diagnoses failing simulation logs, UVM scoreboard mismatches, assertion fires, and VCD/FSDB waveform transitions to isolate RTL root causes.
---

# RTL Regression Debugger Skill

## Purpose
Accelerates ASIC verification debug by analyzing simulation failure transcripts, scoreboard data mismatches, and signal transition dumps, isolating the exact RTL defect.

## When to Activate
Activate when a verification test fails in VCS, Questa, or Xcelium, or an SVA assertion triggers during regression.

## Required Inputs
- Simulation log / error transcript
- Scoreboard comparison mismatch (Expected vs Actual packet)
- Assertion failure message with timestamp and offending signal states
- Offending RTL module source code

## Step-by-Step Workflow
1. **Failure Symptom Categorization:**
   - Scoreboard payload mismatch (data corruption).
   - Dropped transaction / missing beat.
   - Timeout / Deadlock (hang waiting on handshake).
   - Assertion violation (`assert property` fire).
2. **Temporal Alignment:**
   - Map failure timestamp back to the simulation cycle.
   - Trace backwards from the point of observation to the point of generation.
3. **Root-Cause Hypothesis Formulation:**
   - Counter off-by-one error on buffer read/write pointers.
   - Unregistered control signal causing 1-cycle latency skew.
   - Race condition on reset release.
   - Backpressure hazard (dropping data when valid is high and ready deasserts).
4. **Code Inspection & Diagnosis:**
   - Pinpoint the exact line of SystemVerilog code responsible.
5. **Regression Patch:**
   - Provide minimal-impact code fix and companion SVA assertion to prevent regression.

## Technical Constraints
- Never guess missing waveform values; if critical internal states are unlogged, request specific signal dumps from the engineer.

## Output Format
- **Failure Summary:** Test Name | Time of Failure | Failing Signal/Assert
- **Root-Cause Analysis:** Step-by-step tracing of how the bug occurred.
- **Proposed RTL Fix:** Side-by-side code diff.
- **Recommended Regression Test Scenario:** Testbench stimulus to guarantee closure.

## Validation Checklist
- [ ] Fix resolves the failing corner case without perturbing passing tests.
- [ ] No added latency cycles on existing paths.
- [ ] SVA assertion provided to detect future regressions.

## Example Invocation
```text
/rtl-regression-debugger
Test failed: test_axi_backpressure_random
Log: [paste vcs_sim.log excerpt]
Offending module: [paste axi_skid_buffer.sv]
```

---
name: fsm-design-review
description: Evaluates finite state machines for safe encoding (one-hot, binary, Gray), illegal state traps, deadlock recovery, and Moore vs Mealy output timing.
---

# FSM Design Review Skill

## Purpose
Performs comprehensive architectural inspection of SystemVerilog Finite State Machines (FSMs), auditing state encoding choices, illegal state handling, glitch-free output timing, and transition coverage.

## When to Activate
Activate when designing, optimizing, or reviewing sequential control FSMs, protocol controllers, or power management sequencers.

## Required Inputs
- SystemVerilog FSM code (or state diagram / state transition table)
- Performance & Timing goals (Target frequency, critical output latency)
- Target architecture (ASIC vs FPGA)

## Step-by-Step Workflow
1. **FSM Architecture Identification:**
   - Determine if the FSM is Moore (outputs depend only on state) or Mealy (outputs depend on state and inputs).
   - Check if outputs are registered (glitch-free) or combinational (potential timing bottleneck).
2. **Coding Style Audit:**
   - Verify classic 2-process or 3-process FSM coding:
     - Process 1: Sequential state register (`always_ff @(posedge clk ...)`).
     - Process 2: Combinational next-state logic (`always_comb`).
     - Process 3: Registered or combinational output logic.
3. **Encoding Evaluation:**
   - Binary encoding: Compact (minimum flops), good for area-constrained slow control paths.
   - One-hot encoding: 1 bit per state, single gate decode, optimal for high-speed ASIC control paths and FPGAs.
   - Gray encoding: Optimal for sequenced counters with single-bit transitions.
4. **Deadlock & Illegal State Trap Verification:**
   - Verify `default:` branch in next-state decode.
   - For safety-critical designs (automotive, aerospace), check for safe recovery logic to return illegal states to IDLE or ERROR.
5. **Timing & Glitch Elimination:**
   - Flag combinational Mealy outputs routed across module boundaries (can cause long timing arcs and combinational loops).

## Technical Constraints
- Acknowledge that modern synthesis tools (Design Compiler, Genus) can override state encoding via `fsm_encoding` attributes; review both RTL intent and synthesis impact.

## Output Format
- **State Transition Matrix:** Current State | Input Conditions | Next State | Outputs
- **Architecture Evaluation:** Moore vs Mealy, Encoding trade-offs.
- **Identified Defects:** Unreachable states, deadlocks, glitchy outputs.
- **Hardened SystemVerilog Code:** Optimized FSM implementation.

## Validation Checklist
- [ ] Strict use of `typedef enum logic [W-1:0]` for state names.
- [ ] Exhaustive next-state decode with explicit `default`.
- [ ] Outputs are glitch-free and registered where timing critical.
- [ ] Reset state unambiguously defined.

## Example Invocation
```text
/fsm-design-review
Target: 1.2 GHz ASIC control path
Evaluate this SDRAM initialization FSM:
[paste sdram_init_fsm.sv]
```