Carry Lookahead Adder —
No More Waiting for Carry

A full adder computes one bit of sum and carry-out. Chain n of them and you get a ripple carry adder. Simple — but the carry has to ripple from bit 0 all the way to bit n−1. Each full adder must wait for the carry-out of the previous one before it can compute its own carry-out and sum.

Before computing carries in parallel, define two signals per bit position that describe what that position will do with an incoming carry. These two signals, P and G, are computed purely from A and B — no carry needed.

Now substitute the carry recurrence Cᵢ₊₁ = Gᵢ + Pᵢ·Cᵢ into itself repeatedly. Each carry expression expands until it depends only on G, P signals and the original C₀ — never on another carry. All four carries are now computable simultaneously.

Each equation is a sum-of-products (AND-OR) — exactly 2 levels of logic. No matter how wide the adder, every carry is computed with one AND stage and one OR stage. This is the core of CLA speed.

A single 4-bit CLA block has constant carry delay. To build a 16-bit adder, chain four 4-bit CLA blocks. But simply chaining them makes the group carries ripple again. The solution: define Group Generate (GG) and Group Propagate (GP) for each block, then apply CLA logic at the block level too.

Prefix adders generalize CLA using a parallel prefix computation. Define the prefix operator ∘ that combines two (G,P) pairs from adjacent bit groups:

Apply this operator in a binary tree structure. After log₂(n) tree levels, every bit position has a prefix result that gives the carry into that position. Two major implementations trade area vs speed:

Two approaches: explicit gate-level CLA for understanding, and behavioral RTL that lets synthesis infer the optimal structure.

Gate-Level 4-bit CLA

module cla_4bit (
    input  [3:0] A, B,
    input        Cin,
    output [3:0] S,
    output       Cout
);
    wire [3:0] G, P;   // generate, propagate per bit
    wire       C1, C2, C3, C4;

    // PG logic — no carry needed
    assign G = A & B;
    assign P = A ^ B;

    // CLA carry equations (2-level AND-OR)
    assign C1 = G[0] | (P[0] & Cin);
    assign C2 = G[1] | (P[1] & G[0]) | (P[1] & P[0] & Cin);
    assign C3 = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0])
                     | (P[2] & P[1] & P[0] & Cin);
    assign C4 = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1])
                     | (P[3] & P[2] & P[1] & G[0])
                     | (P[3] & P[2] & P[1] & P[0] & Cin);

    // Sum: P XOR carry-in to that bit
    assign S[0] = P[0] ^ Cin;
    assign S[1] = P[1] ^ C1;
    assign S[2] = P[2] ^ C2;
    assign S[3] = P[3] ^ C3;
    assign Cout = C4;

endmodule

32-bit Behavioral (Synthesis Infers CLA)

module adder_32bit (
    input  [31:0] A, B,
    input         Cin,
    output [31:0] S,
    output        Cout
);
    assign {Cout, S} = A + B + Cin;
    // Synthesis tool infers fast carry structure based on timing constraints
    // Set timing constraint tight → Kogge-Stone; relaxed → Brent-Kung
endmodule

Group Propagate/Generate — Building Block for Block CLA

module cla_group_pg (
    input  [3:0] G, P,
    input        Cin,
    output       GG, GP, Cout
);
    // Group generate and propagate for cascaded CLA
    assign GG = G[3] | (P[3]&G[2]) | (P[3]&P[2]&G[1]) | (P[3]&P[2]&P[1]&G[0]);
    assign GP = P[3] & P[2] & P[1] & P[0];
    assign Cout = GG | (GP & Cin);
endmodule

Enter two 4-bit numbers (0–15). Watch how the ripple carry propagates bit by bit vs CLA computing all carries simultaneously. The propagation delay difference is shown visually.