A comprehensive, structured guide to the building blocks of all digital systems — covering Boolean algebra, logic gates, combinational circuits, flip-flops, and number systems with real-world VLSI context.
Each topic builds on the previous one. Start from the top if you're new to digital electronics.
By working through these topics, you'll build the complete foundation expected of a digital design or VLSI engineer.
Convert fluently between binary, hex, octal and understand signed representations used in processor design.
Reduce complex logic expressions using algebraic laws and K-Maps to minimize gate count in hardware.
Build any function using only NAND or NOR gates, and understand how CMOS implements these physically.
Design adders, subtractors, multiplexers, decoders, and understand how carry look-ahead eliminates bottlenecks.
Know how flip-flops store state, why edge-triggering matters, and how metastability affects chip reliability.
Understand how Hamming codes, parity schemes, and LDPC codes protect data in communications and memory.
Understanding digital electronics at this level — not just "AND gate outputs 1 when both inputs are 1" but why, how, and what happens at the physics level — is what separates engineers who can debug chip-level issues from those who can only follow recipes.
Digital circuits use binary — 0 and 1 — not because engineers decided binary was mathematical elegant, but because MOSFET transistors have two stable operating states: fully off (high impedance, output pulled to VDD through a load → logic 1) and fully on (low impedance, output pulled to GND → logic 0). The region between these states — the linear or triode region — is unstable and dissipates power. Digital design keeps transistors out of this region by operating at voltage levels well above or below the switching threshold. This is why digital circuits are noise-immune: a 1.2V signal in a 1.8V system can still be correctly interpreted as logic 1, even with 200mV of noise riding on it.
Boolean algebra — AND, OR, NOT operations on 0 and 1 — is not just abstract math. Each operation corresponds to a specific transistor network. AND corresponds to series NMOS transistors (both must conduct for the output to be pulled low). OR corresponds to parallel NMOS transistors (either can conduct). NOT corresponds to a single inverting stage. NAND and NOR are more efficient than AND and OR because they require fewer transistors (2 vs 3 for a 2-input gate) and are the basis of CMOS standard cell libraries. De Morgan's theorem — that a NAND is equivalent to NOT-OR and a NOR is equivalent to NOT-AND — allows any Boolean expression to be implemented with only NAND or only NOR gates, which is why these are called universal gates.
Combinational logic produces an output that depends only on its current inputs — there is no memory. A 4-to-1 multiplexer, a 4-bit adder, a priority encoder: all combinational. Sequential logic has memory — the output depends on both current inputs and previous state. Flip-flops are the fundamental sequential element: they capture a value on a clock edge and hold it until the next edge. The difference matters for VLSI design because combinational logic has timing paths (data must propagate through all the gates before the next clock edge) while sequential logic creates registers that bound those paths. The balance between combinational and sequential logic — how many stages, how many pipeline registers — is the core of RTL micro-architecture design.
Karnaugh maps provide a visual method for minimizing Boolean expressions — grouping minterms into power-of-2 groups to eliminate variables. Modern synthesis tools (Design Compiler, Genus) do this automatically and much more efficiently than manual K-map analysis for large functions. But understanding K-map minimization — why a group of 4 eliminates 2 variables, why don't-care conditions can reduce logic — builds the mental model for understanding what synthesis tools are doing when they optimize your RTL. An engineer who understands K-maps understands why changing a combinational always block's case statement can reduce the critical path delay, and why the "synthesis attributes" like full_case and parallel_case exist.
Digital electronics is the bedrock on which all modern computing is built. Whether you are designing a microprocessor, programming an FPGA, or verifying an ASIC, every skill traces back to a solid understanding of how transistors implement logic and how logic gates compose into systems.
This section of EcrioniX covers digital electronics with the depth and rigor expected in the semiconductor industry. Each topic is written to serve both students approaching the subject for the first time and working engineers who need a reliable reference. The explanations go beyond defining what each gate does — they explain the physics behind the transistor networks, the mathematical tools for simplifying logic, and the design patterns that lead to efficient, testable, synthesis-friendly digital circuits.
Topics progress naturally from the mathematical foundations (number systems and Boolean algebra) through physical gate implementations, to complete functional units like adders and decoders, and finally to sequential circuits that give hardware its memory and state. Each topic is self-contained but builds on the previous one — starting here and working forward produces a complete digital design foundation.