Static Timing Analysis (STA) is the method used in the semiconductor industry to verify that every timing path in a chip meets its required constraints — without running a single simulation. This section covers STA from first principles to advanced sign-off concepts used in real ASIC tape-out flows.
STA is a simulation method that validates the timing performance of a digital circuit by checking all possible timing paths mathematically — without applying input vectors. It verifies that every signal launches from a flip-flop, travels through combinational logic, and arrives at the next flip-flop with enough margin to meet the clock's setup and hold requirements.
Unlike dynamic simulation, STA is exhaustive — it checks every path simultaneously. This makes it the industry-standard sign-off method for chips running at hundreds of megahertz to multiple gigahertz.
A chip that fails timing will malfunction — wrong data is sampled, computations produce incorrect results, or the system crashes entirely. STA is the last gate before tape-out: no chip ships without meeting all timing constraints across every process, voltage, and temperature (PVT) corner.
Engineers use tools like Synopsys PrimeTime and Cadence Tempus to run STA. Understanding the underlying concepts — setup slack, hold slack, clock skew, OCV, and CPPR — is essential for any physical design or timing closure role.
Topics are organized from foundational concepts to advanced sign-off methodology. Start from Topic 01 if you are new to timing analysis.
STA follows a well-defined sequence of steps to verify every timing path in a design.
The synthesized gate-level netlist is loaded along with timing libraries (.lib) containing cell delay models.
Clock definitions, I/O constraints, and timing exceptions are applied via Synopsys Design Constraints.
The tool constructs a directed acyclic graph (DAG) of all logic paths between sequential elements.
Arrival times and required times are propagated forward and backward through every path in the graph.
Slack = Required Time − Arrival Time. Negative slack means a violation that must be fixed before tape-out.
Understanding these terms is the prerequisite for reading any STA timing report or holding a timing closure discussion.
The margin by which data arrives before the setup requirement deadline. Negative setup slack means the path is too slow for the clock frequency.
The margin by which data remains stable after the clock edge. Hold violations are frequency-independent and require physical fixes.
The spatial variation in clock arrival time across different flip-flops on a chip. Positive skew helps setup; negative skew helps hold.
The temporal uncertainty of when a clock edge actually arrives, caused by power supply noise and thermal effects. Always reduces setup margin.
Accounts for transistor behavior differences across the same die due to local manufacturing imperfections. Addressed with derating factors in STA.
Process (slow/fast), Voltage (low/high), Temperature (hot/cold) combinations that define the worst-case and best-case operating conditions for timing.
Common Path Pessimism Removal. Eliminates impossible pessimism where shared clock buffers are simultaneously modeled as both fast and slow.
A timing path that exists in the netlist but is never logically sensitized during operation. Marked via SDC so the tool does not waste resources fixing it.
Understanding the mechanics behind STA — not just the pass/fail result — is what separates engineers who can fix timing violations from those who just report them.
A setup check asks: does the data signal arrive at the flip-flop input early enough before the capturing clock edge? The STA tool computes the data arrival time — starting from the launch flip-flop's clock edge, adding the clock network delay to that flip-flop's clock pin, adding the flip-flop's clock-to-Q delay, then adding every gate delay on the combinational path to the capture flip-flop's D input.
The tool then computes the required arrival time — the capturing clock edge time minus the setup time of the capture flip-flop, minus any hold margin uncertainty. Setup slack = required time − arrival time. Positive slack means you have margin. Negative slack means the data arrives too late — a violation.
A hold check asks: does the data stay stable long enough after the capturing clock edge? A hold violation occurs when the new data from the same (or next) launch edge arrives too quickly and corrupts the value the flip-flop just captured. The hold check uses the minimum path delay (best-case data) and maximum clock skew (capture clock arrives earliest, giving data less time to be valid).
This is why hold violations are fixed by inserting delay cells (buffers) on the data path — making the minimum data path longer — never by changing the clock period. Fixing hold with frequency changes does not work because both launch and capture edges move together.
A single STA run at nominal conditions tells you nothing about whether the chip will work in the field. In production, chips experience a range of Process (fast/slow silicon), Voltage (low/high supply), and Temperature (hot/cold) variations. Each combination creates a different timing scenario. The slow-slow corner (slow silicon, low voltage, high temperature) is the worst case for setup time — gates are slowest, so data paths take longest. The fast-fast corner (fast silicon, high voltage, low temperature) is the worst case for hold — gates switch fastest, so data can arrive so early it corrupts the previous value before the flip-flop's hold time window closes.
On-Chip Variation (OCV) accounts for the fact that even within a single chip, different parts of the silicon can be faster or slower due to manufacturing variation. STA tools apply derating factors — making the launch path pessimistically slower and the capture path pessimistically faster (for setup) — to guard against this. CPPR (Common Path Pessimism Removal) then removes the artificial pessimism on clock path segments that are shared by both launch and capture paths, since those segments cannot simultaneously be slow AND fast.
STA is only as good as the constraints given to it. The SDC (Synopsys Design Constraints) file tells the timing tool what the clocks are, what the relationships between clocks are, and what timing paths should be analyzed or excluded. A missing create_clock means paths through that domain are not checked. An incorrect set_multicycle_path that assumes a synchronous relationship between two asynchronous clocks will make STA report a passing result for paths that will fail in silicon every time the phase relationship is wrong.
The correct constraint for paths between truly asynchronous clocks is set_clock_groups -asynchronous — this tells STA to not analyze timing between those domains, because the relationship is non-deterministic and must be handled by a synchronizer, not by timing analysis. Every SDC file should be reviewed with the same rigor as RTL code, because an SDC error that disables a timing check is as dangerous as an RTL bug.
Static Timing Analysis is the final verification step that stands between a chip design and silicon fabrication. A design that fails STA sign-off cannot be taped out — no matter how functionally correct the RTL is. This makes STA knowledge essential for every engineer working in digital design, physical design, or design verification.
Unlike simulation, which checks a design for specific input patterns, STA exhaustively checks every timing path simultaneously. This makes it both faster and more thorough. The tradeoff is that STA requires correct constraints — an improperly constrained design may appear to pass timing while hiding real violations.
This section of EcrioniX builds STA knowledge from the ground up — starting with the physical intuition behind setup and hold time, progressing through clock distribution, SDC constraints, and path analysis, and culminating in the timing closure techniques used in real tape-out flows.