How do you build a 4-bit magnitude comparator?

A 4-bit magnitude comparator compares MSB first. A>B if A[3]>B[3], or A[3]=B[3] and A[2]>B[2], etc. The 74HC85 IC implements this with cascade inputs (I_A>B, I_A=B, I_A<B) to chain multiple 4-bit comparators for wider values.

How is a comparator used in digital circuits?

Comparators are used in: sorting networks, priority arbiters (largest value wins), address boundary checking (is address in range?), ALU flag generation (zero flag = all bits equal zero), threshold detectors in ADCs, loop counters (count == MAX), and cache tag comparison (hit/miss detection).

What is a zero detector in digital design?

A zero detector outputs 1 when all input bits are 0. For an N-bit input, it is a NOR gate of all bits: ZERO = NOR(A[N-1:0]) = NOT(A[N-1] OR A[N-2] OR ... OR A[0]). In Verilog: assign zero = (a == 0); or assign zero = ~|a; (the reduction NOR operator). Used for ALU zero flag, loop termination, and equality to zero checks.

Topic 19 · Digital Electronics

Comparators
1-bit · 4-bit · Magnitude

Q: How does a 1-bit comparator work?

A 1-bit equality comparator outputs 1 when A = B, implemented as an XNOR gate: EQ = A XNOR B = NOT(A XOR B). A 1-bit magnitude comparator also outputs A>B (= A AND NOT B) and A<B (= NOT A AND B).

Q: What is the difference between signed and unsigned comparison in Verilog?

In Verilog, by default all signals are unsigned. 8'hFF > 8'h00 is true unsigned (255 > 0). For signed comparison, declare logic signed [7:0] or use $signed(): $signed(8'hFF) < $signed(8'h00) evaluates as -1 < 0, which is true. Without the signed declaration, 8'hFF would be treated as 255 in comparison.

Q: How is a comparator used in digital circuits?

Comparators are used in: sorting networks, priority arbiters (largest value wins), address boundary checking (is address in range?), ALU flag generation (zero flag = all bits equal zero), threshold detectors in ADCs, loop counters (count == MAX), and cache tag comparison (hit/miss detection).

Q: What is a zero detector in digital design?

A zero detector outputs 1 when all input bits are 0. For an N-bit input, it is a NOR gate of all bits: ZERO = NOR(A[N-1:0]) = NOT(A[N-1] OR A[N-2] OR ... OR A[0]). In Verilog: assign zero = (a == 0); or assign zero = ~|a; (the reduction NOR operator). Used for ALU zero flag, loop termination, and equality to zero checks.

Equality and magnitude comparison from the gate level up — including cascading, signed comparison, and common VLSI applications.

XNOR EqualityMagnitude74HC85 CascadingSignedZero DetectorVerilog

1-bit Comparator

A	B	A=B (XNOR)	A>B	A<B
0	0	1	0	0
0	1	0	0	1
1	0	0	1	0
1	1	1	0	0

EQ = A XNOR B | A>B = A · B̄ | A<B = Ā · B

Interactive N-bit Comparator

Input A (0–255)

Input B (0–255)

Signed comparison

Binary: A = B =

A = B

—

A > B

—

A < B

—

Zero (A)

—

4-bit Magnitude Comparator — 74HC85

Compares A[3:0] vs B[3:0] starting from MSB. Cascade inputs (I_A>B, I_A=B, I_A<B) allow chaining: connect outputs of lower chip to cascade inputs of upper chip.

Condition	Output O_A>B	Output O_A=B	Output O_A<B
A > B	1	0	0
A = B (and I_A=B=1)	0	1	0
A < B	0	0	1

For a single 4-bit comparator: set I_A>B=0, I_A=B=1, I_A<B=0

Verilog Comparators

// Unsigned N-bit comparator
module cmp_unsigned #(parameter N=8) (
  input  logic [N-1:0] a, b,
  output logic         eq, gt, lt
);
  assign eq = (a == b);
  assign gt = (a  > b);
  assign lt = (a  < b);
endmodule

// Signed comparison — use $signed() or signed declaration
module cmp_signed #(parameter N=8) (
  input  logic signed [N-1:0] a, b,
  output logic                  eq, gt, lt
);
  assign eq = (a == b);
  assign gt = (a  > b);  // signed comparison
  assign lt = (a  < b);
endmodule

// Zero detector (reduction NOR)
assign zero = ~|a;   // 1 if all bits of a are 0

// 74HC85-style cascadable 4-bit comparator
module cmp4_cascade (
  input  logic [3:0] a, b,
  input  logic       i_gt, i_eq, i_lt,  // cascade in
  output logic       o_gt, o_eq, o_lt   // cascade out
);
  always_comb begin
    if      (a > b) begin o_gt=1; o_eq=0; o_lt=0; end
    else if (a < b) begin o_gt=0; o_eq=0; o_lt=1; end
    else            begin o_gt=i_gt; o_eq=i_eq; o_lt=i_lt; end
  end
endmodule

Comparator Applications

Application	Comparison used
ALU zero flag	~\|result (reduction NOR)
Address range check	addr >= BASE && addr < LIMIT
Priority arbiter	Largest active priority wins
Loop counter termination	count == MAX
Cache tag compare	tag == stored_tag → hit
ADC threshold detect	data > threshold → trigger
Sorting network	Compare-and-swap elements

Frequently Asked Questions

How does a 1-bit comparator work?

EQ = XNOR(A,B). A>B = A AND NOT B. A<B = NOT A AND B. These are the building blocks for wider comparators.

What is the difference between signed and unsigned comparison in Verilog?

Unsigned: 8'hFF = 255 > 0. Signed: 8'hFF = -1 < 0. Declare logic signed [7:0] or use $signed() cast for correct signed comparison.

What is a zero detector?

Outputs 1 when all input bits are 0. In Verilog: assign zero = ~|a; (reduction NOR). Used for ALU zero flag, loop termination, and equality-to-zero checks.

Comparators1-bit · 4-bit · Magnitude