Low Power Double Data Rate memory — the DRAM that powers every smartphone SoC. LPDDR4, LPDDR4X, LPDDR5, LPDDR5X: data rates, bank architecture, timing, PHY interface, and bandwidth calculations explained.
LPDDR (Low Power Double Data Rate) is the mobile-optimized variant of SDRAM. Unlike desktop DDR, LPDDR is designed for:
Operates at 1.05–1.1V (vs 1.2V for DDR4). Includes deep power-down, partial array self-refresh (PASR), and temperature-compensated refresh to minimize idle power in smartphones.
LPDDR dies are stacked directly on top of the SoC in PoP configuration — eliminating long PCB traces and enabling the ultra-thin designs of modern phones.
Dual 32-bit channels give 64-bit effective bus width. LPDDR5X at 8533 Mbps provides 68.3 GB/s — critical for AI inference, 8K video, and gaming workloads.
LPDDR5 adds on-die ECC and link ECC within the PHY — essential for automotive and safety-critical applications running on mobile SoCs.
| Feature | LPDDR4 | LPDDR4X | LPDDR5 | LPDDR5X |
|---|---|---|---|---|
| Max Data Rate | 3200 Mbps | 4267 Mbps | 6400 Mbps | 8533 Mbps |
| VDD (Core) | 1.1V | 1.1V | 1.05V | 1.05V |
| VDDQ (IO) | 1.1V | 0.6V | 0.5V | 0.5V |
| Banks | 8 | 8 | 16 | 16 |
| Bank Groups | None | None | 8 groups × 2 banks | 8 groups × 2 banks |
| Burst Length | BL16/32 | BL16/32 | BL16/32 | BL16/32 |
| Channel Width | 2×16b or 2×32b | 2×16b or 2×32b | 2×16b or 2×32b | 2×16b or 2×32b |
| ECC | None | None | On-die + Link ECC | On-die + Link ECC |
| WCK Clock | No | No | Yes (2× freq) | Yes |
| Peak BW (64b bus) | 25.6 GB/s | 34.1 GB/s | 51.2 GB/s | 68.3 GB/s |
| Typical Device | Snapdragon 845 | A12 Bionic | Snapdragon 888 | A16/Dimensity 9200 |
Bank architecture is critical for performance. Multiple banks allow a memory controller to hide row-precharge latency (tRP) by accessing different banks in parallel.
Flat bank array — no bank groups. tCCD_L (same bank) and tCCD_S (different bank) have a small gap.
16 total banks across 8 groups. Different bank groups allow back-to-back CAS with minimum tCCD (4 cycles) — dramatically improves random access performance.
| Parameter | Full Name | LPDDR5 @ 6400 | Impact |
|---|---|---|---|
| tCL | CAS Latency | 16 cycles | Latency from READ to first data byte |
| tRCD | RAS to CAS Delay | 16 cycles | Delay between ACTIVATE and READ/WRITE |
| tRP | Row Precharge | 16 cycles | Time to close a row — lower = less latency on row miss |
| tRAS | Row Active Strobe | 38 cycles | Minimum time a row stays open |
| tRFC | Refresh Cycle Time | 280 ns | Time memory is unavailable during auto-refresh |
| tCCD_L | CAS-to-CAS (same BG) | 8 cycles | Min gap between two commands to same bank group |
| tCCD_S | CAS-to-CAS (diff BG) | 4 cycles | Min gap between commands to different bank groups |
| tWR | Write Recovery | 22 cycles | Time after last write before precharge allowed |
The PHY (Physical Layer) sits between the memory controller and the LPDDR package. It handles clock generation, DQ training, write-leveling, and impedance matching.
At power-up, the PHY calibrates the DQ-DQS timing alignment using a series of read/write training patterns. LPDDR5 uses a 2D eye scan (voltage + time) for improved margin.
Adjusts output driver impedance and ODT resistance to match PCB characteristic impedance (240Ω). Run at init (ZQ_INIT) and periodically during operation (ZQ_CAL_SHORT).
LPDDR5 introduces WCK — a write clock at 2× the DQ data rate. WCK is forwarded from controller to DRAM to enable the higher 6400+ Mbps data rates.
Command/Address (CA) bus training aligns the CA signal timing to the clock. LPDDR4/5 use a CA Vref training step to center the CA input level at the DRAM.
// Simplified LPDDR5 command issue FSM (one bank, one channel) // Real controllers have full command scheduler, bank tracking, tRAS enforcement typedef enum logic [2:0] { IDLE, ACTIVATE, TRCD_WAIT, ISSUE_READ, TCL_WAIT, DATA_OUT, PRECHARGE } lpddr_state_t; lpddr_state_t state_q; logic [7:0] timer_q; always_ff @(posedge clk) begin if (!rst_n) begin state_q <= IDLE; timer_q <= '0; cmd_valid <= 1'b0; end else begin case (state_q) IDLE: if (rd_req) begin state_q <= ACTIVATE; cmd_valid <= 1'b1; cmd <= CMD_ACT; // send ACTIVATE row_addr <= req_row; end ACTIVATE: begin cmd_valid <= 1'b0; timer_q <= TRCD - 1; // TRCD = 16 for LPDDR5 @ 6400 state_q <= TRCD_WAIT; end TRCD_WAIT: begin timer_q <= timer_q - 1; if (timer_q == 0) state_q <= ISSUE_READ; end ISSUE_READ: begin cmd_valid <= 1'b1; cmd <= CMD_RD; col_addr <= req_col; timer_q <= TCL - 1; // TCL = 16 state_q <= TCL_WAIT; end TCL_WAIT: begin cmd_valid <= 1'b0; timer_q <= timer_q - 1; if (timer_q == 0) state_q <= DATA_OUT; end DATA_OUT: begin // BL32: 16 DQ cycles × 2 (DDR) = 32 bytes per burst rd_data_valid <= 1'b1; state_q <= PRECHARGE; end endcase end end
| Mode | Power | Wake-up Latency | Use Case |
|---|---|---|---|
| Active (RW) | ~500–800 mW | 0 | Normal operation — CPU/GPU accessing memory |
| Idle (CLK off) | ~50 mW | <1 µs | Short idle between bursts |
| Self-Refresh (SR) | ~5–15 mW | ~5 µs | Screen-off, light sleep — retains all data |
| PASR (Partial SR) | ~2–8 mW | ~5 µs | Refresh only populated array portion |
| Deep Power-Down | <1 mW | ~200 µs | Hibernate / data-retention not required |
LPDDR (Low Power Double Data Rate) is mobile-optimized SDRAM. It operates at lower voltages (1.05–1.1V vs 1.2V for DDR4), includes deep power-down modes, and is packaged in PoP (Package-on-Package) stacked directly on the SoC. Used in every smartphone, tablet, and modern IoT device.
LPDDR5 offers 2× the data rate (6400 vs 3200 Mbps), 16 banks vs 8 (organized as 8 bank groups), a new WCK clock for signal integrity, on-die and link ECC for reliability, and 0.5V VDDQ (vs 1.1V) for lower power. LPDDR5X pushes further to 8533 Mbps.
LPDDR5 at 6400 Mbps with a 64-bit bus (standard 2-channel config): 6400 Mbps × 64 bits / 8 = 51.2 GB/s peak. At 85% efficiency = ~43.5 GB/s effective. LPDDR5X at 8533 Mbps reaches 68.3 GB/s peak.
tCL: CAS latency — cycles from READ command to first data. tRCD: RAS-to-CAS — cycles between ACTIVATE and READ/WRITE. tRP: Row Precharge — cycles to close a row before opening another. These three parameters (together written as tCL-tRCD-tRP) define the core access latency.
ZQ calibration adjusts the LPDDR device's output driver impedance and ODT resistance to match the PCB's characteristic impedance (240Ω reference). It compensates for PVT (process, voltage, temperature) variations. ZQ_INIT runs at startup; ZQ_CAL_SHORT runs every few milliseconds during operation.
LPDDR uses lower voltages (1.05V vs 1.2V DDR4), has mobile-specific power modes (PASR, TCSR, deep power-down), uses a different connector/package (PoP vs DIMM), has a dedicated CA bus (LPDDR5), and is not physically interchangeable with desktop DDR. LPDDR prioritizes power; desktop DDR prioritizes raw bandwidth.