What is a memory array and how does address decoding work?

A memory array organizes bit cells in a 2D grid of rows × columns. An N-bit address selects 2^N rows. The address is split: row address activates a word line (selects an entire row), column address selects which bit(s) to read/write via column mux and sense amplifiers. For a 1K×8 RAM: 10-bit address, 3 bits select column (8 bits wide), 7 bits select row (128 rows), each row holds 8 bits.

What is the difference between synchronous and asynchronous RAM?

Asynchronous RAM responds immediately when address/enable signals change — no clock needed. Synchronous RAM samples address, data, and control signals on the clock edge — output appears one cycle later. Synchronous RAM is universally preferred in modern digital design because it integrates cleanly into clocked pipelines and is easier to time-analyze. All modern SRAMs (register files, caches) are synchronous.

What is a ROM and what are the different types?

ROM (Read-Only Memory) stores fixed data written at manufacture or programming time. Types: Mask ROM (programmed at fab — cheapest for high volume), OTP ROM (One-Time Programmable — fused once by user), EPROM (Erasable with UV light), EEPROM (Electrically erasable byte-by-byte), Flash (electrically erasable in blocks — used in SSDs, microcontrollers). All ROM types provide non-volatile storage — data survives power-off.

What is cache memory and why is it needed?

Cache is a small, fast SRAM buffer between the CPU and slow main memory (DRAM). The CPU runs at ~3–4 GHz but DRAM latency is ~100 ns (300+ cycles). A 3-level cache hierarchy: L1 (32KB, 1-4 cycles, on-chip), L2 (256KB-1MB, 10-20 cycles), L3 (8-32MB, 30-50 cycles) exploits temporal and spatial locality — keeping frequently used data close to the CPU. Cache hit rate above 95% is typical for most workloads.

What is a dual-port RAM and when is it used?

A dual-port RAM has two independent access ports (each with its own address, data, and control signals) so two operations can occur simultaneously. True dual-port (TDP) allows simultaneous read+write to different addresses. Simple dual-port (SDP) has one read port and one write port. Used in register files (CPU), video frame buffers, FIFOs, and ping-pong buffers for producer/consumer designs.

Topic 18 · Digital Electronics

SRAM vs DRAM
Memory Arrays · Cache · Verilog

Q: What is the difference between SRAM and DRAM?

SRAM (Static RAM) uses 6 transistors per cell in a cross-coupled inverter latch — it holds data as long as power is applied without refreshing, has fast access (< 1 ns in caches), but is large and expensive. DRAM (Dynamic RAM) uses 1 transistor + 1 capacitor per cell — 6× denser and cheaper, but the capacitor leaks and must be refreshed every ~64 ms. SRAM is used for CPU caches; DRAM is used for main memory (DDR4/DDR5).

From the 6-transistor SRAM cell to DDR5 DRAM, ROM types, cache hierarchy, and synthesizable Verilog RAM/ROM — everything you need to master digital memory.

SRAM 6T CellDRAMROM / Flash Cache L1/L2/L3Array OrganizationVerilog

SRAM vs DRAM — Core Comparison

SRAM — Static RAM

6 transistors per bit (cross-coupled inverters)
No refresh needed — holds data as long as power on
Access time: 1–5 ns (cache speed)
Large area — ~50–150 F² per bit
Used in: CPU caches, register files, FPGAs, on-chip RAMs

DRAM — Dynamic RAM

1 transistor + 1 capacitor per bit
Capacitor leaks → must refresh every ~64 ms
Access time: 60–100 ns (with tRCD/tCL)
Dense — ~6–8 F² per bit, 6× cheaper than SRAM
Used in: main memory (DDR4, DDR5, LPDDR5)

Parameter	SRAM	DRAM
Cell transistors	6 (+ access transistors)	1T1C
Refresh required	No	Yes (~64 ms)
Typical access time	1–5 ns	60–100 ns
Density	Low (~6× less than DRAM)	High
Power	Higher (static leakage)	Lower per bit
Volatile	Yes	Yes
Primary use	CPU cache, register file	Main memory (DDR)

SRAM 6T cell: Two cross-coupled CMOS inverters (4 transistors) hold the bit — stable as long as power is on. Two NMOS access transistors connect to the bit lines when the word line is asserted. Reading uses differential sense amplifiers on the complementary bit lines.

Memory Array Organization

A memory with 2^N words × W bits wide has:

Parameter	Formula	Example: 1K×8
Address bits	N = log₂(words)	N = 10 bits
Total bits	words × W	1024 × 8 = 8192 bits
Row select (word line)	2^(N−log₂W)	128 word lines
Column select	log₂(W)	3 bits → 8 columns
Sense amplifiers	W per row	8

Why 2D array? A pure 1D array of 1024 cells would need 1024 sense amplifiers — too many. A 2D array folds rows into columns: 128 rows × 8 columns needs only 8 sense amplifiers. The row decoder selects a row (word line), then the column mux selects the output bit.

Interactive 8×8 RAM Simulator

Address (0–63): Data (hex):

Click a cell to select. Green = written. Blue highlight = selected.

Address 0x00 → 0x3F (64 bytes, 8 columns wide)

ROM Types

Type	Programming	Erasable	Typical Use
Mask ROM	At fabrication	No	High-volume embedded firmware
OTP ROM	Once by user (fuse)	No	Security keys, one-time config
EPROM	Electrically	UV light (whole chip)	Legacy — replaced by EEPROM
EEPROM	Electrically	Electrically (byte)	BIOS, config data, small NVM
NAND Flash	Electrically	Block erase	SSD, microSD, USB drives
NOR Flash	Electrically	Block erase	Code execution (XIP), MCU flash

Flash has limited write endurance: NAND ~10K–100K writes per block, NOR ~100K writes per byte. Wear-leveling algorithms spread writes evenly across blocks to maximize lifetime.

Cache Memory Hierarchy

CPU Registers

~16–256 regs · <1 ns · on-die

L1 Cache (SRAM)

32–64 KB · 1–4 cycles · on-die per core

L2 Cache (SRAM)

256 KB–2 MB · 10–20 cycles · on-die per core

L3 Cache (SRAM)

8–64 MB · 30–60 cycles · shared on-die

Main Memory (DRAM — DDR5)

8–128 GB · 100–300 cycles · off-chip

Cache hit rate >95% is typical. A miss at L1 goes to L2, then L3, then DRAM. Each level is ~10× slower and ~10× larger than the one above it.

Verilog — Synchronous RAM & ROM

Synchronous Single-Port RAM

// Synchronous RAM: write on clock edge, read registered
module ram_sp #(
  parameter WORDS = 1024,
  parameter W     = 8,
  parameter ADDR  = 10  // log2(WORDS)
) (
  input  logic             clk,
  input  logic [ADDR-1:0] addr,
  input  logic [W-1:0]    wdata,
  input  logic             we,
  output logic [W-1:0]    rdata
);
  logic [W-1:0] mem [0:WORDS-1];

  always_ff @(posedge clk) begin
    if (we) mem[addr] <= wdata;
    rdata <= mem[addr];   // read-first (old data)
  end
endmodule

True Dual-Port RAM

// True dual-port: two independent read/write ports
module ram_tdp #(parameter WORDS=1024, W=8, ADDR=10) (
  input  logic             clk,
  input  logic [ADDR-1:0] addra, addrb,
  input  logic [W-1:0]    wdataa, wdatab,
  input  logic             wea, web,
  output logic [W-1:0]    rdataa, rdatab
);
  logic [W-1:0] mem [0:WORDS-1];
  always_ff @(posedge clk) begin
    if (wea) mem[addra] <= wdataa;
    if (web) mem[addrb] <= wdatab;
    rdataa <= mem[addra];
    rdatab <= mem[addrb];
  end
endmodule

ROM (Lookup Table)

// ROM: initialized with $readmemh or inline case
module rom_lut #(parameter W=8, DEPTH=256, ADDR=8) (
  input  logic [ADDR-1:0] addr,
  output logic [W-1:0]    rdata
);
  logic [W-1:0] mem [0:DEPTH-1];
  initial $readmemh("rom_init.hex", mem);  // load from file
  assign rdata = mem[addr];  // combinational read
endmodule

// Or inline initialization for small ROMs
always_comb case (addr[3:0])
  4'h0: rdata = 8'h3F; // 7-seg '0'
  4'h1: rdata = 8'h06; // 7-seg '1'
  // ...
  default: rdata = 8'h00;
endcase

Frequently Asked Questions

What is the difference between SRAM and DRAM?

SRAM: 6T cell, no refresh, 1–5 ns, large area → caches. DRAM: 1T1C, refresh every 64 ms, 60–100 ns, dense → main memory.

What is synchronous vs asynchronous RAM?

Synchronous RAM is clocked — data output appears one cycle after address. Asynchronous RAM outputs immediately. All modern designs use synchronous for clean timing analysis.

What is a dual-port RAM used for?

Two independent access ports allow simultaneous read+write. Used in register files, FIFOs, video buffers, ping-pong buffers, and any producer/consumer architecture.

What is the difference between NAND and NOR flash?

NAND flash is denser and cheaper — used for mass storage (SSDs). NOR flash supports random byte reads and execute-in-place (XIP) — used for MCU code storage where CPU executes directly from flash.

SRAM vs DRAMMemory Arrays · Cache · Verilog