What is pipelining in digital design?

Pipelining divides a long combinational path into multiple shorter stages separated by registers. Each stage processes a different data item simultaneously, like an assembly line. This increases throughput (operations per second) at the cost of higher latency (time for one item to complete). A k-stage pipeline can process k items simultaneously, ideally achieving k× the throughput of the unpipelined design.

What is the difference between latency and throughput in a pipeline?

Latency is the time for a single input to produce its output — in a k-stage pipeline it is k × Tclk (k clock cycles). Throughput is the rate of output production — ideally 1 output per clock cycle (Fmax outputs/second) once the pipeline is full. Pipelining trades latency for throughput: each item takes longer to complete, but the steady-state output rate is much higher.

What are pipeline hazards?

Pipeline hazards are situations that prevent the next instruction or data from executing in the next clock cycle. Data hazard: a stage needs a result not yet produced by a previous stage (RAW, WAR, WAW dependencies). Structural hazard: two stages need the same hardware resource simultaneously. Control hazard: a branch/jump changes the flow before the pipeline has fetched the correct next instruction.

What is data forwarding (bypassing)?

Data forwarding (also called bypassing) resolves RAW data hazards without stalling the pipeline. Instead of waiting for a result to be written to a register file and then read, the result is forwarded directly from the output of one pipeline stage to the input of a later stage that needs it. Forwarding paths are added as multiplexers that select between the register file output and the forwarded value.

When do you need to stall a pipeline?

A stall (bubble) is inserted when a hazard cannot be resolved by forwarding. The most common case is a load-use hazard: when an instruction reads memory (load) and the immediately following instruction needs that value — the load result is not available until after the memory stage, so one stall cycle is required even with forwarding. Control hazards (branches) often stall until the branch outcome is resolved, or use branch prediction to speculate.

How do you implement a pipeline register in Verilog?

A pipeline register is a set of flip-flops between two combinational stages that capture all intermediate signals on the clock edge. In Verilog: always_ff @(posedge clk) begin if (stall) /* hold */ else if (flush) pipe_reg <= '0; else pipe_reg <= {sig_a, sig_b, sig_c}; end. The stall signal holds the register (freeze stage), flush inserts a bubble for branch misprediction recovery.

Topic 17 · Digital Electronics

Pipelining in Digital Design
Stages · Hazards · Throughput

How to multiply throughput by splitting long paths into stages — and how to handle the hazards that arise when stages interact.

Pipeline StagesLatency vs Throughput Data HazardForwardingStall Control HazardVerilog

What is Pipelining?

Without pipelining, the next computation can only start after the current one fully completes — the entire combinational path must settle. Pipelining inserts registers between stages, letting each stage work on a different data item every clock cycle, like a factory assembly line.

Throughput = 1 output / T_clk (steady state) | Latency = k × T_clk (k stages)

Interactive Pipeline Simulator

Include stall cycle:

Clock

Completed

Throughput

—

Efficiency

—

Throughput Calculator

Pipeline stages (k)5

T_logic per stage (ns)2 ns

T_overhead / stage (ns)0.2 ns

Stall cycles / 1005%

Fmax

—

Throughput

—

Latency

—

Speedup vs. 1-stage

—

Pipeline Hazards

Hazard Type	Cause	Resolution
Data — RAW Read-After-Write	Stage N needs a value being written by stage N-1	Forwarding (bypass), or stall if load-use
Data — WAR Write-After-Read	Stage N writes a register that stage N-1 hasn't read yet	Rare in in-order pipelines; register renaming in OOO
Data — WAW Write-After-Write	Two stages both write the same destination	Stall or register renaming
Structural	Two stages need the same hardware (e.g., one memory port)	Separate instruction/data memories; dual-port RAM
Control	Branch/jump changes PC before fetched instructions are correct	Flush misfetched instructions; branch prediction; delay slot

Load-Use Hazard (must stall)

LW R1, 0(R2)
IFIDEXMEMWB
ADD R3, R1, R4
IFIDSTALLEXMEMWB
R1 not available until end of MEM stage — ADD must wait one cycle (even with forwarding)

Verilog — Pipeline Register

// 3-stage pipeline: IF → EX → WB
module pipeline3 #(parameter W=32) (
  input  logic         clk, rst_n, stall, flush,
  input  logic [W-1:0] if_data,
  output logic [W-1:0] wb_result
);
  logic [W-1:0] if_ex, ex_wb;

  // IF → EX pipeline register
  always_ff @(posedge clk or negedge rst_n) begin
    if      (!rst_n) if_ex <= '0;
    else if (flush)  if_ex <= '0;   // bubble on branch flush
    else if (!stall)  if_ex <= if_data; // hold on stall
  end

  // EX stage: combinational logic (e.g., ALU)
  logic [W-1:0] ex_out;
  assign ex_out = if_ex + 1;   // placeholder ALU op

  // EX → WB pipeline register
  always_ff @(posedge clk or negedge rst_n) begin
    if      (!rst_n) ex_wb <= '0;
    else if (flush)  ex_wb <= '0;
    else if (!stall)  ex_wb <= ex_out;
  end

  assign wb_result = ex_wb;
endmodule

Forwarding Logic (RAW Hazard Resolution)

// Forward EX/MEM result back to EX stage input
always_comb begin
  // Forward from EX/MEM pipeline register
  if (ex_mem_regwrite && ex_mem_rd != 0 &&
      ex_mem_rd == id_ex_rs1)
    alu_a = ex_mem_aluout;      // forward from EX/MEM
  // Forward from MEM/WB pipeline register
  else if (mem_wb_regwrite && mem_wb_rd != 0 &&
           mem_wb_rd == id_ex_rs1)
    alu_a = mem_wb_result;      // forward from MEM/WB
  else
    alu_a = id_ex_rs1_val;      // use register file
end

// Load-use stall detection
assign load_use_stall = id_ex_memread &&
  (id_ex_rd == if_id_rs1 || id_ex_rd == if_id_rs2);

Pipeline Performance Analysis

Speedup = k / (1 + stall_fraction × k) (ideal: Speedup → k for large N)

Design	T_logic	Stages	T_clk	Fmax	Stalls	Effective throughput
Unpipelined	10 ns	1	10 ns	100 MHz	—	100 Mop/s
5-stage (ideal)	2 ns	5	2 ns	500 MHz	0%	500 Mop/s
5-stage (10% stall)	2 ns	5	2 ns	500 MHz	10%	450 Mop/s
5-stage (30% stall)	2 ns	5	2 ns	500 MHz	30%	350 Mop/s

Amdahl's Law applies: pipeline speedup is limited by the portion of time stalled. A 5-stage pipeline with 30% stalls achieves only 3.5× speedup, not 5×. Reducing hazards (forwarding, branch prediction) is essential.

Frequently Asked Questions

What is pipelining and why use it?

Pipelining splits a long combinational path into k shorter stages with registers between them. Each stage runs in parallel on different data — achieving up to k× throughput at the cost of k× latency.

What is the difference between a data hazard and a control hazard?

Data hazard: a later stage needs a value a previous stage hasn't produced yet (RAW/WAR/WAW). Control hazard: a branch changes the program counter while the pipeline has already fetched wrong instructions.

Can you always fix a data hazard with forwarding?

No — load-use hazards require one stall cycle even with forwarding, because the load result isn't available until after the memory stage. Forwarding can eliminate all other RAW hazards.

How do you implement a stall in Verilog?

Hold all pipeline registers upstream of the stalled stage (freeze the data), and insert a bubble (all-zero control signals) into the stalled stage's output register: if (!stall) pipe_reg <= next; // else hold

Pipelining in Digital DesignStages · Hazards · Throughput