What is setup time and hold time in digital design?

Setup time (Tsu) is the minimum time the data input must be stable BEFORE the clock edge for the flip-flop to reliably capture it. Hold time (Th) is the minimum time data must remain stable AFTER the clock edge. Violating setup time causes the output to be undefined on the current cycle. Violating hold time causes corruption from the next input value bleeding in before the FF has latched the current value.

What is slack in timing analysis?

Slack is the margin between the required arrival time and the actual arrival time of a signal. Setup slack = (clock period - setup time - clock-to-Q delay - combinational delay). Hold slack = (actual arrival time - hold time - clock skew). Positive slack means timing is met. Negative slack (a timing violation) means the design will fail at that frequency and must be fixed before tapeout or FPGA programming.

What is a critical path in a digital circuit?

The critical path is the longest combinational logic path between any two registers in the design — it determines the maximum operating frequency. Fmax = 1 / (Tclk_to_Q + Tlogic + Tsetup + Tskew). To run faster you must shorten the critical path: pipeline it (add a register in the middle), retime (move registers), or reduce logic depth (use faster gates or restructure the Boolean function).

What is clock skew and how does it affect timing?

Clock skew is the difference in arrival time of the clock edge at different flip-flops. Positive skew (destination FF gets clock later) tightens setup but relaxes hold. Negative skew (destination FF gets clock earlier) relaxes setup but tightens hold — can cause hold violations. Clock tree synthesis (CTS) in physical design minimizes skew by balancing the clock distribution network.

What is the difference between static and dynamic timing analysis?

Static timing analysis (STA) exhaustively analyzes all timing paths using worst-case delay models without simulation — fast, complete, no test vectors needed. It checks setup, hold, and pulse-width across all paths. Dynamic timing analysis (gate-level simulation with timing) simulates actual input sequences and is slower, incomplete (depends on coverage), but can find timing-dependent logic bugs that STA misses. Industry uses STA as the primary sign-off method.

What are SDC timing constraints?

SDC (Synopsys Design Constraints) is the industry-standard format for specifying timing constraints to synthesis and STA tools. Key commands: create_clock (define clock period and waveform), set_input_delay (arrival time of inputs relative to clock), set_output_delay (required time for outputs), set_false_path (ignore timing on specific paths), set_multicycle_path (allow paths to take multiple clock cycles), set_max_delay / set_min_delay (explicit delay bounds).

How do you fix a setup timing violation?

Setup violations mean the path is too slow. Fixes: (1) Pipeline — insert a register to break the long path in half, (2) Retime — move registers to balance path lengths, (3) Logic restructuring — reduce levels of logic (e.g., use carry-lookahead instead of ripple carry), (4) Cell upsizing — replace slow cells with faster (larger) drive-strength equivalents, (5) Route optimization — reduce wire delay on critical nets, (6) Lower clock frequency as a last resort.

Topic 16 · Digital Electronics

Timing Analysis
Setup · Hold · Slack · STA

The core of every digital sign-off — understand timing paths, calculate slack, fix violations, and write SDC constraints.

Setup TimeHold TimeSlack Critical PathClock SkewJitter STASDC Constraints

Setup Time & Hold Time

Parameter	Definition	Consequence if violated
Setup time (T_su)	Min time data must be stable BEFORE clock edge	FF output undefined this cycle — metastability
Hold time (T_h)	Min time data must be stable AFTER clock edge	New data bleeds in — FF captures wrong value
Clock-to-Q (T_cq)	Propagation delay from clock edge to Q output	Increases path delay, reduces Fmax
Propagation delay (T_pd)	Combinational logic delay between two FFs	Longer paths → lower Fmax

Timing Path Anatomy

FF (launch)
──Tcq──►
Combo Logic
──Tpd──►
FF (capture)
Data must arrive at capture FF no later than (Tclk − Tsu) and no earlier than Th after the clock edge

Setup slack = T_clk − T_cq − T_pd − T_su − T_skew

Hold slack = T_cq + T_pd,min − T_h + T_skew

Interactive Timing Diagram & Slack Calculator

Adjust parameters — watch slack change live

Clock period (T_clk) 10 ns

Clock-to-Q (T_cq) 1 ns

Combo delay (T_pd) 5 ns

Setup time (T_su) 1 ns

Hold time (T_h) 0.5 ns

Clock skew 0 ns

Setup Slack

—

Hold Slack

—

Fmax

—

Status

—

Critical Path & Maximum Frequency

F_max = 1 / (T_cq + T_pd,max + T_su + T_skew)

The critical path is the timing path with the worst (smallest) setup slack. It limits Fmax for the entire design.

Fix	Method	Reduces
Pipelining	Insert FF to split long path in half	T_pd
Retiming	Move registers across combinational logic	T_pd
Logic restructuring	CLA instead of RCA, Shannon decomposition	T_pd
Cell upsizing	Replace with faster (higher drive) cell	T_pd
Route optimization	Buffer insertion, shorter wire on critical net	T_pd
Reduce skew	Better CTS, use clock gating cells	T_skew

Clock Skew & Jitter

Parameter	Definition	Effect on timing
Skew	Arrival time difference between launch and capture FF clocks	Positive skew: tightens setup, relaxes hold. Negative skew: opposite.
Jitter	Cycle-to-cycle variation in clock period	Reduces effective timing margin — must be budgeted in STA
Clock uncertainty	STA margin = skew + jitter	Subtracted from setup slack budget

Hold violations are clock-frequency independent — they are caused by paths that are too FAST, not too slow. Adding pipeline stages makes hold violations worse. Fix hold with buffer insertion on the short path.

Static Timing Analysis (STA) Flow

1Elaborate netlist — synthesis produces a gate-level netlist from RTL
2Read constraints (SDC) — define clocks, I/O delays, false paths, multicycle paths
3Apply parasitics (SPEF) — wire delays from physical layout
4Run STA — tool propagates delays, computes slack for every path
5Fix violations — pipeline/retime/upsize until all slack ≥ 0

SDC Timing Constraints

# Define 500 MHz clock on port clk
create_clock -period 2.0 -name clk [get_ports clk]

# Input arrives 0.5 ns after clock edge
set_input_delay  -clock clk -max 0.5 [get_ports {data_in reset_n}]
set_input_delay  -clock clk -min 0.1 [get_ports {data_in reset_n}]

# Output must arrive 0.3 ns before next clock edge
set_output_delay -clock clk -max 0.3 [get_ports data_out]

# Ignore async reset path (no timing required)
set_false_path -from [get_ports rst_async]

# Allow 2 clock cycles for the divide path
set_multicycle_path -setup 2 -from [get_cells u_div/*] -to [get_cells u_acc/*]
set_multicycle_path -hold  1 -from [get_cells u_div/*] -to [get_cells u_acc/*]

# Clock uncertainty (jitter + skew budget)
set_clock_uncertainty -setup 0.1 [get_clocks clk]
set_clock_uncertainty -hold  0.05 [get_clocks clk]

Verilog Timing Checks (Simulation)

// $setup and $hold system tasks in specify block
specify
  $setup(data, posedge clk, 1.0);   // 1 ns setup
  $hold (posedge clk, data, 0.5);   // 0.5 ns hold
  $setuphold(posedge clk, data, 1.0, 0.5);  // combined
endspecify

// Timing check in testbench (self-checking)
always @(posedge clk) begin
  if ($time - last_data_change < T_SETUP)
    $error("Setup violation at %0t", $time);
end

Fixing Timing Violations

Violation	Root Cause	Fix
Setup violation	Path too slow (T_pd too large)	Pipeline, retime, upsize cells, restructure logic
Hold violation	Path too fast (T_pd too small)	Add buffers on short path — never add pipeline stage
Skew violation	Clock tree imbalanced	Rebalance CTS, use clock buffers, reduce fanout
Pulse-width violation	Clock duty cycle distorted	Fix PLL, use BUFGCE, check inverter chain

Common mistake: Trying to fix a hold violation by pipelining makes it worse — pipeline adds more Tcq delay at the launch end, making the short path even shorter relative to hold time. Fix hold with delay buffers only.

Golden rule: Setup violations → reduce delay. Hold violations → add delay. They require opposite fixes.

Frequently Asked Questions

What is setup time and hold time?

Setup time: data must be stable this long BEFORE the clock edge. Hold time: data must remain stable this long AFTER the clock edge. Violating either causes metastability or data corruption.

What is slack? Can slack be negative?

Slack = timing margin. Positive slack = timing met with margin. Negative slack = timing violation — the design will fail at that clock frequency and cannot be fabricated/programmed as-is.

What is the difference between STA and simulation?

STA is exhaustive (all paths, no test vectors) and fast. Simulation depends on test coverage and is slower but finds logic bugs. Industry uses STA for sign-off timing and simulation for functional verification.

How do you fix a hold violation?

Insert delay buffers on the short (fast) path. Never add pipeline stages — that makes hold worse. Hold violations are frequency-independent: they exist at any clock speed.

Timing AnalysisSetup · Hold · Slack · STA