Graded Verilog problems

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Graded problems

Wire the Input Straight to the Output

Verilog Language Basics · combinational, basics — Connect a single input to a single output with a continuous assignment.

2-Input AND Gate

Verilog Language Basics · combinational, gates — Build a 2-input AND gate. Output is 1 only when both inputs are 1.

2-to-1 Multiplexer

Combinational Design · combinational, mux — Select between two 1-bit inputs using sel. When sel=0 output a; when sel=1 output b.

1-Bit Full Adder

Combinational Design · combinational, arithmetic — Compute sum and carry-out for a + b + cin.

4-to-1 Multiplexer

Combinational Design · combinational, mux — Select one of four 1-bit inputs using a 2-bit sel. sel=00→in0, 01→in1, 10→in2, 11→in3.

4-to-2 Priority Encoder

Combinational Design · combinational, encoder — Output the index of the highest-priority (MSB-most) set bit in a 4-bit input, plus a valid flag when any bit is set.

D Flip-Flop with Asynchronous Reset

Sequential Design · sequential, flip-flop — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.

4-Bit Shift Register (SIPO)

Sequential Design · sequential, shift-register — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.

1-Bit Half Adder

Combinational Design · combinational, adder — The building block behind every adder chain: add two single bits and produce a sum and a carry-out.

2-to-4 Line Decoder

Combinational Design · combinational, decoder — Turn a 2-bit address into a one-hot 4-bit select line, gated by an enable input.

4-Bit Magnitude Comparator

Combinational Design · combinational, comparator — Compare two 4-bit unsigned numbers and flag whether the first is greater than, equal to, or less than the second.

BCD to 7-Segment Decoder

Combinational Design · combinational, display — Drive a 7-segment display from a 4-bit BCD digit (0-9). The kind of decoder inside every digital clock and calculator.

8-Bit Even Parity Generator

Combinational Design · combinational, parity — Generate a parity bit so that data plus parity always has an even number of 1s — the simplest error-detection scheme in digital design.

4-Bit Ripple Carry Adder

Combinational Design · combinational, adder — Add two 4-bit numbers plus a carry-in, producing a 4-bit sum and carry-out — the width-extended sibling of the half adder.

Sequential Design · sequential, flip-flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.

4-Bit Up/Down Counter

Sequential Design · sequential, counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

Modulo-6 Counter

Sequential Design · sequential, counter — A counter that wraps back to 0 after reaching 5, instead of overflowing at the natural binary boundary — the pattern behind clock dividers and digit counters.

Sequence Detector: 1011 (Overlapping)

Sequential Design · sequential, fsm — A Moore FSM that watches a serial bit stream and pulses high for one cycle right after it spots the pattern 1011 — overlapping matches count.

1-Bit Full Subtractor

Combinational Design · combinational, subtractor — Subtract b and a borrow-in from a, producing a difference bit and a borrow-out — the subtraction twin of the full adder.

Binary to Gray Code Converter

Combinational Design · combinational, code-converter — Convert a 4-bit binary number into its Gray code equivalent, where only one bit ever changes between consecutive values.

Gray to Binary Code Converter

Combinational Design · combinational, code-converter — Reverse the conversion: turn a 4-bit Gray code value back into standard binary.

8-to-3 Priority Encoder

Combinational Design · combinational, encoder — The wider sibling of the 4-to-2 priority encoder: pick the index of the highest-priority set bit among 8 request lines.

Combinational Design · combinational, alu — Build a small arithmetic-logic unit: add, subtract, AND, or OR two 4-bit numbers based on a 2-bit opcode, plus a zero flag.

8-Bit Barrel Rotator

Combinational Design · combinational, shifter — Rotate an 8-bit value left by a variable amount in a single combinational step — no loops, no clock.

3-Input Majority Voter

Combinational Design · combinational, voter — Output 1 whenever at least two of the three inputs agree — the logic behind triple-modular-redundancy fault tolerance.

4-Bit Gray Code Counter

Sequential Design · sequential, counter, gray-code — A counter whose output is always valid Gray code, changing only one bit per clock — used to safely cross clock domains.

4-Bit Linear Feedback Shift Register

Sequential Design · sequential, lfsr — A self-shifting register that generates a pseudo-random bit sequence — the core of BIST pattern generators and simple scramblers.

4-Bit Shift Register (PISO)

Sequential Design · sequential, shift-register — Parallel-in, serial-out shift register — load a nibble in one cycle, then read it out one bit at a time, MSB first.

4-Bit Universal Shift Register

Sequential Design · sequential, shift-register — One register, four behaviors: hold, shift left, shift right, or parallel load, all picked by a 2-bit mode select.

Pulse Stretcher

Sequential Design · sequential, pulse — Turn a single 1-cycle pulse into a guaranteed 3-cycle-wide output pulse — the kind of circuit that makes a fast event visible to a slow observer.

Sequence Detector: 101 (Non-Overlapping)

Sequential Design · sequential, fsm — A Moore FSM detecting the pattern 101 on a serial stream — but unlike the overlapping 1011 detector, a match here consumes all three bits before searching resumes.

Traffic Light Controller

Sequential Design · sequential, fsm — A timer-driven Moore FSM that cycles a single intersection through RED, GREEN, and YELLOW on fixed schedules — the classic FSM-with-a-counter pattern.

Vending Machine FSM (15-Cent)

Sequential Design · sequential, fsm — A classic textbook FSM: accept nickels and dimes, and dispense as soon as the running total reaches 15 cents (no change given).

8-Bit Population Count

Combinational Design · combinational, algorithmic — Count how many of the 8 input bits are set to 1 — the building block behind ECC, Hamming weight, and bit-similarity checks.

4-Bit Signed Overflow Detector

Combinational Design · combinational, arithmetic — Add two 4-bit two's-complement numbers and flag whether the result overflowed the representable signed range.

Find First Set Bit

Combinational Design · combinational, algorithmic — Find the index of the lowest-numbered set bit in an 8-bit input — the LSB-first counterpart to a priority encoder.

2-Flop CDC Synchronizer

Sequential Design · sequential, cdc — Safely bring an asynchronous signal into a clock domain using two cascaded flip-flops — the standard first line of defense against metastability.

Divide-by-3 Clock Pulse

Sequential Design · sequential, clock — Generate a pulse that fires once every 3 input clock cycles — dividing by a non-power-of-2 needs a counter, not a toggle flip-flop.

Combination Lock FSM

Sequential Design · sequential, fsm — Unlock only after seeing the exact code sequence 2 → 1 → 3, entered one digit per clock. Any wrong digit resets progress — except digit 2, which can restart a fresh attempt on the spot.

4-Way Round-Robin Arbiter

Sequential Design · sequential, arbiter — Grant a shared resource to one of four requesters each cycle, rotating priority so nobody gets starved by a persistently high-priority neighbor.

8-Bit Binary to 3-Digit BCD (Double Dabble)

Combinational Design · combinational, algorithmic — Convert an 8-bit binary number (0-255) into three separate BCD digits — hundreds, tens, ones — using the classic shift-and-add-3 algorithm.

Manchester Encoder

Combinational Design · combinational, protocol — Combine a data bit with the clock to produce a Manchester-encoded line signal — the self-clocking encoding used in classic Ethernet and RFID.

Priority Interrupt Controller

Sequential Design · sequential, controller — Latch incoming interrupt requests, present the highest-priority pending one to the CPU, and clear it only when explicitly acknowledged — even if the request line drops before that.

8-Bit Odd Parity Checker

Combinational Design · combinational, parity — Check whether a received byte plus its parity bit together carry an odd number of 1s — the receiving half of an odd-parity error-detection scheme.

BCD to Excess-3 Converter

Combinational Design · combinational, code-converter — Convert a BCD digit (0-9) into Excess-3 code, a self-complementing code once used in early decimal computers.

4-Bit Add/Subtract Unit

Combinational Design · combinational, arithmetic — One adder, two operations: a single control bit selects between a+b and a-b using the standard invert-and-add-one trick.

8-to-1 Multiplexer

Combinational Design · combinational, mux — The next step up from 2:1 and 4:1 — select one of eight inputs using a 3-bit select line.

3-to-8 Line Decoder

Combinational Design · combinational, decoder — The 3-bit sibling of the 2-to-4 decoder — turn a 3-bit address into a one-hot 8-bit select line, gated by enable.

4-Bit Carry Lookahead Adder

Combinational Design · combinational, arithmetic — Compute all four carries in parallel from generate/propagate signals instead of rippling them one bit at a time — the classic fix for ripple-carry's O(N) delay.

8-Bit Equality Checker

Combinational Design · combinational, comparator — A dedicated equal-only comparator for two 8-bit buses — the cheap end of the comparator family, no subtractor required.

4-Bit Array Multiplier

Combinational Design · combinational, arithmetic — Multiply two 4-bit numbers into an 8-bit product — the operation an array multiplier builds from a grid of AND gates and adders.

BCD Digit Adder

Combinational Design · combinational, arithmetic — Add two BCD digits (0-9) plus a carry-in and produce a valid BCD digit result — binary addition alone isn't enough once the sum exceeds 9.

4:2 Carry-Save Compressor

Combinational Design · combinational, arithmetic — Reduce five weight-1 inputs (four data bits plus a carry-in) down to a sum bit and two weight-2 outputs — the building block that makes fast multiplier reduction trees possible.

Sequential Design · sequential, flip-flop — A set/reset flip-flop with a well-defined answer for the "both asserted" case that the classic SR latch leaves undefined.

D Latch (Level-Sensitive)

Sequential Design · sequential, latch — A transparent latch: while enable is high, the output follows the input instantly; once enable drops, the last value is held — no clock edge involved.

4-Bit Johnson Counter

Sequential Design · sequential, counter — A twisted-ring counter that walks through 2N unique states by shifting in the inverted MSB each cycle — a different rhythm from a plain ring or binary counter.

4-Bit Ring Counter

Sequential Design · sequential, counter — A single active bit walks around a 4-bit register, wrapping back to the start — the one-hot counter used to sequence states with zero decode logic.

4-Bit Saturating Up/Down Counter

Sequential Design · sequential, counter — A counter that clamps at its limits instead of wrapping — pushing further up at 15 or further down at 0 simply has no effect.

Sequential Design · sequential, timer — A timeout that fires unless it keeps getting "kicked" — the safety-net circuit that resets a hung system when its heartbeat stops arriving.

Streaming Frame Parity Checker

Sequential Design · sequential, parity — Accumulate the running parity of a serial bit stream one bit per clock, resetting cleanly at the start of every 8-bit frame.

Programmable Clock Divider

Sequential Design · sequential, clock — A generalized version of divide-by-3: the division amount is set by a runtime input instead of being hardwired into the design.

Push/Pop Stack Pointer

Sequential Design · sequential, pointer — A 4-bit stack pointer that moves up on push and down on pop, refusing to overflow past 15 or underflow past 0.

Button Debouncer

Sequential Design · sequential, debounce — Filter out mechanical switch bounce: only pass a button input through once it has held the same value for 3 consecutive clock cycles.

Hamming(7,4) Encoder

Combinational Design · combinational, ecc — Encode 4 data bits into a 7-bit Hamming codeword that can detect and correct any single-bit error — the error-correcting code behind ECC memory.

Hamming(7,4) Decoder

Combinational Design · combinational, ecc — Take a Hamming(7,4) codeword — possibly corrupted by a single flipped bit — and recover the correct data, flag the error, and report exactly which position was wrong.

4-to-8 Bit Sign Extension

Combinational Design · combinational, arithmetic — Widen a 4-bit two's-complement number to 8 bits while preserving its value — a trap many beginners fall into by zero-extending instead.

8-Bit Saturating Adder

Combinational Design · combinational, arithmetic — Add two unsigned bytes, but clamp the result at 255 instead of silently wrapping around — the kind of arithmetic DSP and audio-level circuits actually want.

Rock, Paper, Scissors Judge

Combinational Design · combinational, game — Given both players' moves, decide the winner in a single combinational step — a fun exercise in translating a small rule set into conditional logic.

One's-Complement Checksum Adder

Combinational Design · combinational, arithmetic — Add two bytes using end-around-carry addition — the exact arithmetic behind the Internet checksum used in IP, TCP, and UDP headers.

4-Bit MIPS-Style ALU

Combinational Design · combinational, alu — Build the classic MIPS ALU: AND, OR, add, subtract, and set-less-than, selected by the actual 3-bit control codes a real MIPS ALU control unit generates.

Population Count Comparator

Combinational Design · combinational, algorithmic — Not "which number is bigger" — "which number has more 1 bits set". A comparator built on top of a bit-counting core instead of magnitude.

Manchester Decoder

Combinational Design · combinational, protocol — Recover the original data bit from a Manchester-encoded line signal — the exact inverse of the Manchester Encoder problem.

Digital Dice (LFSR)

Sequential Design · sequential, lfsr — An LFSR-powered dice roller: advance a maximal-length 3-bit LFSR each cycle and map its output into a valid 1-6 range.

2-Floor Elevator Controller

Sequential Design · sequential, fsm — A simplified elevator FSM: sit idle until called, take one cycle to transit between floors, and only move when actually requested.

Quadrature Rotary Encoder Decoder

Sequential Design · sequential, protocol — Decode the two-phase A/B signal from a real rotary knob or mouse wheel into a direction and position count — sample B on every rising edge of A.

Sequential Design · sequential, clock — Generate a pulse-width-modulated output with a programmable duty cycle out of 16 — the technique behind LED dimming and motor speed control.

Synchronous 8x8 RAM

Sequential Design · sequential, memory — A minimal single-port RAM: 8 words of 8 bits each, with a registered (one-cycle-delayed) read — the standard timing behavior of real block RAM.

Combination Safe with Lockout

Sequential Design · sequential, fsm — A combination lock that locks itself out entirely after 3 failed attempts — a security-flavored extension of the basic combination lock FSM.

FIFO Occupancy Counter

Sequential Design · sequential, fifo — Track exactly how many words are sitting in an 8-deep FIFO — not just full/empty booleans, but the actual live count, including the tricky case of a simultaneous push and pop.

2-Digit 7-Segment Multiplexer

Sequential Design · sequential, display — Drive two digits from one shared set of segment lines by rapidly alternating which digit is active — the real technique behind every multi-digit 7-segment display.

BCD Stopwatch (00-59 Seconds)

Sequential Design · sequential, counter — Two chained BCD digits counting seconds from 00 to 59 and wrapping — the real digit-chaining pattern behind every digital clock and stopwatch display.

Alarm Clock Trigger

Sequential Design · sequential, comparator — Fire an alarm for exactly one cycle the moment the current time matches the alarm time — not for the entire minute the clock happens to sit on that value.

Traffic Light with Pedestrian Crossing

Sequential Design · sequential, fsm — Extend the basic traffic light FSM with a pedestrian crossing button: a press latches a request that cuts the green phase short instead of waiting out the full cycle.

Fixed-Priority Arbiter

Combinational Design · combinational, encoder — Grant exactly one of four requesters at a time, always favoring the highest-index request when several arrive together.

Two's-Complement Negator

Combinational Design · combinational, arithmetic — Negate a signed 4-bit number and correctly flag the one input value that cannot be negated.

Interrupt Vector Generator

Combinational Design · combinational, encoder — Turn up to four pending interrupt lines into a fixed 8-bit vector table address, always dispatching the highest-priority IRQ first.

Sign-Magnitude to Two's-Complement Converter

Combinational Design · combinational, arithmetic — Convert a 4-bit sign-magnitude number (top bit = sign, bottom 3 bits = magnitude) into standard two's-complement.

2-Digit BCD to Binary Converter

Combinational Design · combinational, arithmetic — Convert two separate BCD digits (tens and units) into their actual binary decimal value, 0-99.

BCD Up/Down Counter

Sequential Design · sequential, counter — A single-digit BCD counter that wraps at 9 going up and at 0 going down — not at the binary limits of a 4-bit register.

Registered Change Detector

Sequential Design · sequential, edge-detect — Flag combinationally, in the very same cycle, whenever the input differs from its last-registered value.

Rising-Edge Frequency Counter

Sequential Design · sequential, edge-detect — Count the number of rising edges seen on a pulse input while a measurement window is open — not the number of cycles it happens to sit high.

Two-Way Traffic Intersection

Sequential Design · sequential, fsm — Control two perpendicular traffic lights so that only one direction is ever green or yellow at a time — a safety-critical mutual-exclusion FSM.

UART Frame Assembler

Sequential Design · sequential, fsm, communication — Detect a UART start bit on a serial line, shift in 8 data bits LSB-first, and flag the completed byte for exactly one cycle.

4-to-8 Bit Gearbox

Sequential Design · sequential, datapath — Pack two 4-bit nibbles arriving one per cycle into a single 8-bit word, pulsing valid only once the pair is complete — the narrow-to-wide half of a SerDes gearbox.

8-to-4 Bit Gearbox

Sequential Design · sequential, datapath — Split an 8-bit word into two 4-bit nibbles, emitting the high nibble one cycle and the low nibble the next — the wide-to-narrow half of a SerDes gearbox.

CRC-4 Generator

Combinational Design · combinational, protocol — Compute the 4-bit CRC remainder of an 8-bit message using the CRC-4 (poly x⁴+x+1) bit-serial algorithm, entirely in combinational logic.

Combinational Design · combinational, protocol — Recompute the CRC-4 remainder of a received message and compare it against the appended CRC field to flag transmission errors.

Additive LFSR Scrambler

Sequential Design · sequential, lfsr, protocol — Whiten a data stream by XORing it with a free-running LFSR keystream — the same circuit that descrambles it, since XOR is its own inverse.

Run-Length Bit Stuffer

Sequential Design · sequential, protocol — Flag when a stuff bit must be inserted after five consecutive 1s in a serial stream — the core rule behind CAN bus bit stuffing.

AXI-Stream Handshake Counter

Sequential Design · sequential, protocol — Count how many beats have actually transferred across a valid/ready handshake — a transfer only happens when both sides agree, not whenever the source merely asserts valid.

Byte Sync Detector

Sequential Design · sequential, protocol — Lock onto a known sync byte in an incoming byte stream and stay locked afterward — the framing step every byte-oriented receiver needs before it can trust word boundaries.

16-Bit Endianness Swapper

Combinational Design · combinational, datapath — Swap the byte order of a 16-bit word — the wiring fix needed whenever two datapaths disagree on big-endian vs little-endian byte order.

Packet Length Counter

Sequential Design · sequential, protocol — Count how many cycles a frame stayed active and latch that length the moment the frame ends — resetting cleanly so the next frame's length isn't polluted by the last one.

Async-Assert / Sync-Deassert Reset

Sequential Design · sequential, cdc — Assert reset the instant it goes active, but only release it once it has been clean for 2 clock edges — the standard reset architecture for any real design.

3-Flop CDC Synchronizer

Sequential Design · sequential, cdc — A deeper 3-stage synchronizer for signals that need extra MTBF margin beyond the standard 2-flop chain.

Synchronized Rising-Edge Detector

Sequential Design · sequential, cdc, edge-detect — Safely synchronize an asynchronous level signal, then produce a clean single-cycle pulse the moment it rises in the local clock domain.

Toggle-Based Pulse Synchronizer

Sequential Design · sequential, cdc — Cross a single-cycle pulse safely between clock domains by toggle-encoding it — a plain 2-flop level synchronizer would simply miss it if the destination clock is slower.

CDC Handshake Acknowledge Responder

Sequential Design · sequential, cdc, protocol — Synchronize an asynchronous request line and fire exactly one acknowledge pulse per request — never re-acking while the request is still held, only re-arming once it drops.

Stretch-and-Synchronize Pulse

Sequential Design · sequential, cdc — Widen a fast, possibly very short pulse to guarantee it's caught by a much slower destination clock, then synchronize the stretched level cleanly across domains.

CDC Bus Hold Register

Sequential Design · sequential, cdc, datapath — Capture a data bus only on a valid strobe and hold it steady otherwise — never let an unregistered async bus pass straight through to downstream logic.

Synchronized-Enable Counter Snapshot

Sequential Design · sequential, cdc — Snapshot a free-running counter's value only when an asynchronous sample request has been safely synchronized — synchronizing the control signal, not the fast-changing data, is the trick.

Async-FIFO Empty Flag Synchronizer

Sequential Design · sequential, cdc, protocol — Synchronize a Gray-coded write pointer into the read domain and compare it against the local read pointer to generate a reliable empty flag — the core of every async FIFO.

Async-FIFO Full Flag Synchronizer

Sequential Design · sequential, cdc, protocol — Synchronize a Gray-coded read pointer into the write domain and compare it against the local write pointer to detect full — including the extra wrap-bit check the empty flag never needs.

Combinational Design · combinational, datapath — Reverse the bit order of an 8-bit word so the LSB becomes the MSB and vice versa — pure rewiring, no arithmetic.

Leading Zero Counter (CLZ)

Combinational Design · combinational, encoder — Count how many leading zero bits sit above the highest set bit in an 8-bit value — the CLZ primitive behind floating-point normalization and priority schedulers.

Hex 7-Segment Decoder

Combinational Design · combinational, display — Extend a BCD 7-segment decoder to the full hexadecimal range 0-F — the driver every FPGA dev-board hex display actually needs.

Thermometer-to-Binary Encoder

Combinational Design · combinational, encoder — Convert a thermometer-coded value (a run of 1s from the LSB, as produced by a flash ADC comparator bank) into its binary magnitude.

Binary-to-Thermometer Decoder

Combinational Design · combinational, decoder — Convert a binary magnitude into a thermometer code — the decoder behind every LED bar-graph level meter.

BCD Digit Validator

Combinational Design · combinational, arithmetic — Flag whether a 4-bit nibble is a legal BCD digit (0-9) or one of the six unused patterns (10-15) — the guard every BCD datapath needs before trusting its input.

SPI Full-Duplex Shift Register

Sequential Design · sequential, protocol — Build the core shift register behind SPI: transmit a byte MSB-first while simultaneously receiving one, both directions moving on the same clock edge.

I2C Start/Stop Condition Detector

Sequential Design · sequential, protocol, i2c — Detect the two conditions that frame every I2C transaction: SDA falling while SCL is high (START) and SDA rising while SCL is high (STOP) — the one rule that makes I2C's bus protocol work at all.

Thermostat with Hysteresis

Sequential Design · sequential, fsm — Control a heater with a dead-band between the on and off thresholds, so it doesn't chatter on and off every time the temperature crosses a single setpoint.

3-Tap FIR Filter

Sequential Design · sequential, datapath — Implement a fixed-coefficient 3-tap FIR filter (1,2,1) over a signed input stream — the multiply-accumulate structure behind every digital smoothing/anti-aliasing filter.

UART Transmitter

Sequential Design · sequential, protocol, fsm — Frame a byte onto a UART line: start bit, 8 data bits LSB-first, stop bit — the transmit-side complement to this catalog's UART frame assembler.

4-Bit Signed Multiplier

Combinational Design · combinational, arithmetic — Multiply two 4-bit two's-complement numbers into a correctly-signed 8-bit product — the exact same * operator as an unsigned multiplier, but only if every operand and the output are actually declared signed.

Median of Three

Combinational Design · combinational, comparator — Find the median (middle) value of three unsigned bytes — a classic three-way comparison building block used everywhere from sorting networks to median filters.

Combinational Design · combinational, comparator — Find both the minimum and maximum of three unsigned bytes at once — the basic building block of any sorting network or range check.

Combinational Design · combinational, arithmetic — Subtract two BCD digits and produce a valid BCD result plus a borrow flag — the complement to this catalog's BCD adder.

Shift-Add Multiplier

Sequential Design · sequential, datapath — Multiply two unsigned 4-bit numbers using the classic shift-add algorithm — one bit of the multiplier examined per cycle, exactly how early CPUs implemented multiplication in hardware before dedicated multiplier arrays.

Auto-Repeat Button

Sequential Design · sequential, control — Fire an immediate pulse the instant a button is pressed, then keep firing repeat pulses at a steady interval for as long as it stays held — the key-repeat behavior behind every keyboard.

Gray Code Sequence Checker

Sequential Design · sequential, checker — Watch a stream of 4-bit values and flag whether each new sample really is a valid Gray-code step from the last one — exactly one bit changed, no more, no less.

One-Shot Pulse Generator

Sequential Design · sequential, control — Turn a trigger into a clean pulse of a fixed, programmable width — a classic monostable ("one-shot") that ignores any retrigger attempts until the current pulse finishes.

Serial-to-Parallel Receiver with Parity

Sequential Design · sequential, protocol — Receive an 8-bit word one bit at a time, MSB first, followed by an even-parity check bit — and flag a mismatch instead of silently trusting corrupted data.

Count Leading Ones (CLO)

Combinational Design · combinational, encoder — Count how many leading one bits sit at the top of an 8-bit value before the first zero — the complement to this catalog's leading-zero counter.

4-Bit Signed Comparator

Combinational Design · combinational, comparator — Compare two 4-bit two's-complement numbers and flag greater-than, equal, or less-than — the signed counterpart to this catalog's unsigned 4-bit comparator.

8-Bit Barrel Shifter

Combinational Design · combinational, datapath — Shift an 8-bit value left by a variable amount, filling the vacated low bits with zero — the non-wrapping cousin of this catalog's barrel rotator.

BCD Incrementer

Combinational Design · combinational, arithmetic — Add one to a BCD digit, wrapping 9 back to 0 with a carry — the combinational building block behind every BCD counter on this site.

4-Sample Moving Average Filter

Sequential Design · sequential, datapath — Compute a running average over the last 4 samples of a stream — the simplest possible smoothing filter, and a shift-register-plus-adder pattern that shows up constantly in sensor and audio pipelines.

Countdown Timer with Pause

Sequential Design · sequential, control — A loadable countdown timer that can be paused and resumed mid-count without losing its place — the difference between a real pause and quietly ignoring the pause button.

True Dual-Port RAM

Sequential Design · sequential, memory — An 8x8 memory with two fully independent read/write ports on the same clock — the structure behind every register file and dual-port block RAM.

2-Way LRU Tracker

Sequential Design · sequential, cache — Track which of two cache ways was least recently used with a single bit — the tiny piece of state behind LRU replacement in a 2-way set-associative cache.

Valid/Ready Skid Buffer

Sequential Design · sequential, protocol, datapath — Absorb one cycle of downstream backpressure without dropping data — the 1-entry buffer that makes a ready/valid handshake safe to pipeline.

Dual-Edge-Triggered Flip-Flop

Sequential Design · sequential, fundamentals — Capture data on both the rising and falling edge of the clock — the DDR-style flop behind double-data-rate memory interfaces.

4-Bit Binary Counter

Sequential Design · sequential, counter — Synchronous 4-bit up-counter with active-high reset. Counts on posedge clk; reset clears to 0.

Rising Edge Detector

Sequential Design · sequential, edge — Pulse out high for one clock when din rises 0→1. Sync to clk; ignore din otherwise.

T Flip-Flop (Enable Toggle)

Sequential Design · sequential, fsm — When t=1, toggle q each clock. When t=0, hold. Sync reset clears q to 0.

Rock Paper Scissors Lizard Spock

Fun & Games · combinational, game-logic — Judge a round of the 5-way expanded rock-paper-scissors from The Big Bang Theory — each move beats exactly two of the other four, so the usual 3-way rule table isn't enough.

Magic 8-Ball Fortune Teller

Fun & Games · sequential, lfsr — Give a "random-feeling" fortune-teller answer on every shake using a self-advancing 3-bit LFSR — a tiny, deterministic taste of pseudo-randomness in hardware.

Hot Potato Token Passer

Fun & Games · sequential, fsm, game-logic — Pass a token around a 4-player ring every cycle until a buzzer sounds — whoever's holding it when the music stops loses, and the game freezes there.

Reaction Game Scorer

Fun & Games · sequential, fsm, game-logic — Score a simple reflex game: a light comes on, the player presses a button, and the circuit measures how many cycles it took — flagging jumping the gun or dozing off.

Space Invaders Collision Detector

Fun & Games · combinational, comparator — Detect whether a bullet hits an alien: a classic range-overlap check dressed up as retro arcade collision logic.

Quiz Show Buzzer Lockout

Fun & Games · sequential, arbiter, game-logic — Build a 4-player quiz buzzer: whoever presses first wins and locks out everyone else until the host resets — first-to-press, not round-robin.

Tug of War Position Tracker

Fun & Games · sequential, counter, game-logic — Track the rope's position in a tug-of-war: each pull nudges a signed counter one way, and crossing a threshold declares a winner instantly.

Parking Garage Spot Counter

Fun & Games · sequential, counter — Track available spots in an 8-space garage as cars enter and exit, refusing to go negative when it's already full — an up/down counter with real-world guard rails.

Hamming Distance Calculator

Fun & Games · combinational, error-correction — Count how many bit positions differ between two 8-bit values — the core distance metric behind error-correcting codes like Hamming(7,4).

Slot Machine Jackpot Detector

Fun & Games · combinational, comparator — Judge a 3-reel slot machine spin: jackpot when all three reels match, a smaller near-miss flag when exactly two do.

4-Bit Carry-Select Adder

Combinational Design · combinational, arithmetic, architecture — Speed up addition by precomputing the upper half twice — once assuming carry-in 0, once assuming carry-in 1 — then muxing in whichever guess turned out right, instead of waiting for the carry to ripple through.

Radix-4 Booth Encoder

Combinational Design · combinational, arithmetic, multiplier — The lookup table at the heart of every fast hardware multiplier: examine 3 overlapping bits of the multiplier and decide whether to add 0, ±1x, or ±2x of the multiplicand this cycle — halving the number of partial products versus naive shift-and-add.

Signed Absolute Value (4-bit)

Combinational Design · combinational, arithmetic, signed — Negate a signed 4-bit number to get its magnitude — except for the one input where negating it doesn't fit back into 4 bits at all.

Clamp Value to Range

Combinational Design · combinational, datapath — Saturate a value into [lo, hi] — the single most-used guard clause in DSP, graphics, and safety-critical datapaths.

Integer Square Root

Combinational Design · combinational, arithmetic — Compute floor(sqrt(in)) for an 8-bit input using a bank of perfect-square threshold comparisons — no division, no iteration.

CRC-8 Generator (poly 0x07)

Protocols & Interfaces · combinational, error-correction, protocol — Compute an 8-bit CRC over a byte using the classic 0x07 polynomial (CRC-8-CCITT) — the same bit-serial algorithm behind this catalog's CRC-4, scaled up to a full byte.

Numerically Controlled Oscillator (NCO)

Sequential Design · sequential, clock-generation — Generate a square wave of a programmable frequency from one fixed clock, using nothing but a free-running phase accumulator — the same trick behind DDS frequency synthesizers.

SPI Mode Selector (CPOL/CPHA)

Protocols & Interfaces · combinational, protocol — Decode SPI's 4 clocking modes from CPOL and CPHA into the two facts a controller actually needs: what the clock idles at, and which edge samples data.

Direct-Mapped Cache Lookup

Sequential Design · sequential, memory, cache — A 4-line direct-mapped cache that auto-allocates on a miss — the tag-compare-and-fill loop every real cache runs, shrunk down to something you can trace by hand.

4-Entry Content-Addressable Memory (CAM)

Sequential Design · combinational, memory — Search all 4 stored entries in parallel for a key — the associative-lookup structure behind TLBs and packet-classification hardware.

3-Read / 1-Write Register File

Sequential Design · sequential, memory, datapath — The classic RTL building block behind every processor datapath: 8 registers, one synchronous write port, and three fully independent asynchronous read ports.

Bit Interleaver (Morton-Style)

Combinational Design · combinational, bit-manipulation — Weave two 4-bit values together bit-by-bit into an 8-bit result — the core operation behind Morton (Z-order) codes used to turn 2D coordinates into a single cache-friendly index.

Bit Deinterleaver

Combinational Design · combinational, bit-manipulation — Undo an interleaved byte back into its two original 4-bit streams — the inverse of this catalog's bit interleaver.

Binary to One-Cold Decoder

Combinational Design · combinational, decoder — Decode a 3-bit select into an active-low one-cold output — the polarity every chip-select and enable line on real silicon actually uses.

8-Bit Maximal-Length LFSR

Sequential Design · sequential, lfsr — Scale this catalog's 4-bit LFSR up to a full byte — 8 bits, 4 feedback taps, and a 255-state cycle before it repeats.

Simon Says Sequence Checker

Fun & Games · sequential, fsm, game-logic — Check a player's button presses against a fixed 4-step target sequence, one press at a time — freeze on the first mistake, celebrate after the last correct press.

Parking Meter Timer

Fun & Games · sequential, counter, fsm — A coin-fed countdown timer that flags a violation the instant time runs out and no more coins arrive — a real-world countdown-with-guard pattern.

Top-3 Leaderboard Tracker

Fun & Games · sequential, comparator, datapath — Maintain the 3 highest scores seen so far in sorted order as new scores stream in — an insertion-sort shift register in miniature.

Leap Year Checker

Fun & Games · combinational, arithmetic — Determine whether a given year is a leap year — the classic "divisible by 4, except by 100, except-except by 400" rule as combinational logic.

FizzBuzz Encoder

Fun & Games · combinational, arithmetic — The classic programming-interview puzzle, recast as combinational hardware: classify a number as Fizz, Buzz, FizzBuzz, or itself.

APB Slave Register Interface

Protocols & Interfaces · sequential, protocol, amba — A minimal AMBA APB slave: 4 registers, zero wait states — and the two-phase setup/access handshake that decides exactly when a write is allowed to land.

AXI4-Lite Write Channel FSM

Protocols & Interfaces · sequential, protocol, amba, fsm — Accept an address+data write beat, then hold the response channel until the master acknowledges — the handshake FSM behind every AXI4-Lite peripheral.

AXI4-Lite Read Channel FSM

Protocols & Interfaces · sequential, protocol, amba, fsm — The read-side twin of this catalog's AXI4-Lite write FSM: accept an address, then hold the data response until the master accepts it.

Integrated Clock Gating Cell (ICG)

Sequential Design · combinational, clock-generation, low-power — The standard cell every low-power design leans on to disable a clock branch without ever producing a runt pulse — a level-sensitive latch, not a plain AND gate.

Interrupt Mask Register

Combinational Design · combinational, interrupt — Gate a bank of interrupt sources through a per-bit mask so that masked-off interrupts never reach the CPU — the register-level building block behind every real interrupt controller.

Brown-Out Reset Detector

Sequential Design · sequential, power, reset — Trigger a reset when the supply voltage dips too low — and use two different thresholds for asserting vs. releasing it, so noise near the edge can't chatter the reset line.

Power-On Reset (POR) Generator

Sequential Design · sequential, reset, counter — Hold every flop in reset for a fixed number of cycles after power-up before releasing them — the counter-based POR sitting between a raw power rail and the rest of a chip.

Low-Power Sleep/Wake FSM

Sequential Design · sequential, fsm, low-power — Enter a low-power sleep state on request and wake on an interrupt — but never actually go to sleep if a wake interrupt is already pending the instant sleep is requested.

Bus Timeout Watchdog

Sequential Design · sequential, counter, protocol — Flag an error if a bus transaction doesn't get a ready response within a fixed number of cycles — and make sure that error actually clears once a transaction succeeds.

Lockstep Dual-Core Comparator

Sequential Design · sequential, safety — The functional-safety watchdog behind lockstep processors: compare two redundant cores' outputs every cycle, and once they ever disagree, latch that fault permanently.

Register-Map Address Decoder

Combinational Design · combinational, decoder — Decode a bus address into one of 8 register chip-selects — and correctly refuse to assert anything for out-of-range addresses instead of aliasing them.

Credit-Based Flow Control Counter

Sequential Design · sequential, counter, protocol — Track available send credits so a sender never transmits more than the receiver has buffer space for — the flow-control mechanism behind NoC and high-speed serial links.

Weighted Round-Robin Arbiter

Sequential Design · sequential, arbiter — Give one requester more grants per round than the other — the QoS-style arbiter behind bandwidth allocation in NoCs and shared-memory controllers.

AXI-Stream Packet Counter

Protocols & Interfaces · sequential, protocol, amba — Count completed packets on an AXI-Stream by watching tlast — but only when a beat is actually accepted, not just whenever tlast happens to be asserted.

DMA Descriptor Beat Counter

Sequential Design · sequential, counter, dma — Track remaining beats in a DMA transfer as they complete, guarding against the stray late-arriving pulse that real pipelined DMA engines can produce after completion.

Over-Temperature Throttle Monitor

Sequential Design · sequential, power, monitor — Throttle performance at a warning temperature and shut down entirely at a critical one — with a recovery margin so the chip doesn't oscillate in and out of shutdown right at the edge.

Voltage Margin Monitor

Combinational Design · combinational, monitor, power — Flag a fault when the supply voltage strays outside its safe band in either direction — over-voltage or under-voltage, either one is a problem.

JTAG TAP Instruction Decoder

Combinational Design · combinational, dft — Decode a JTAG TAP controller's instruction register — with the one spec rule that trips up most first attempts: every unimplemented code must default to BYPASS.

Scan Chain Shift Register

Sequential Design · sequential, dft — A 4-flop scan chain that captures functional data in normal operation but shifts a test pattern straight through when scan mode is enabled — the DFT structure behind every ATPG test on real silicon.

Power Rail Sequencer

Sequential Design · sequential, fsm, power — Bring up 3 power rails one at a time in a fixed order — and bring them down in the exact reverse order, since powering down the rail others depend on first can damage real silicon.