← Problems Hub Learning Paths Skill Assessment Leaderboard
Part of Curriculum: Advanced SoC and Chiplet RTL (Module 9: UCIe Sideband Link Initialization FSM)
View Full Roadmap →
Level 6 Industry Challenge ★ Advanced #53 50 pts ✓ Solved

Educational Chiplet Link Initialization & Sideband Training FSM

Advanced RTL & Protocol Design · advanced-rtl, ucie-and-chiplet-architecture, systemverilog, asic, fpga

Design an educational link-training finite state machine inspired by UCIe sideband handshaking, link configuration, and error recovery.

Module Specification
Write a synthesizable Verilog module named top_module matching the ports below exactly.
📐 Circuit Schematic Diagram
NEXT STATECOMBINATIONALSTATE REG[D-FF / CLK]OUTPUTLOGICinit_startlink_req_outcurrent_state [Feedback Loop]>clk, rst
⚡ Timing & Synthesizability Constraints

Timing Contract: Clocked on posedge clk with active-low rst_n. Timeout counter fires after 8 consecutive cycles stuck in LINK_TRAIN without partner response.

RTL Constraints: Clear educational protocol abstraction. Synthesizable Verilog-2001.

Objective: Implement a 7-state chiplet link initialization controller: RESET, INIT_REQ, LINK_TRAIN, CONFIG, ACTIVE, ERROR, and RECOVERY. Coordinate bidirectional handshaking with a partner die (partner_req, partner_ack, train_done), monitor link timeouts, and support fault recovery without full system reset.

Prerequisites: UCIe / PCIe link training concepts, sideband state machines, timeout monitoring, hardware fault recovery.
Port Contract
PortDirWidthDescription
clk, rst_ninput1Clock and active-low synchronous reset
init_startinput1Host processor command to bring up chiplet link
partner_req, partner_ackinput1Handshake signals received from opposite die
train_pattern_okinput1PHY signal indicating PRBS bit-lock achieved
error_detectedinput1Parity/CRC fault trigger
link_req_out, link_ack_outoutput1Handshake signals transmitted to opposite die
link_active, link_erroroutput1Status flags for active transmission and error
state_out[2:0]output3Current FSM state: 0=RESET, 1=REQ, 2=TRAIN, 3=CFG, 4=ACTIVE, 5=ERR, 6=RECOVERY
Expected Waveform (Golden Timing Contract)
💡 Need Guidance? Progressive Hints (3 Levels)
Hint 1: Conceptual Direction & Hardware Primitives
Use a 3-bit state register encoding states 0 through 6.
Hint 2: Implementation Architecture & Approach
Increment timeout_cnt only while in ST_TRAIN. If it reaches 7 without train_pattern_ok, transition to ST_ERROR.
Hint 3: Edge Cases, Timing & Verilog Syntax
ST_ERROR transitions to ST_RECOVERY on the next clock, which in turn returns to ST_REQ to retry link training.
🔒 Reveal Verified Reference RTL Solution (Click to expand)
⚠️ Self-Discovery Warning: Try solving and simulating first! Viewing the verified reference implementation will bypass the real debugging experience.
Verified Synthesizable RTL 
module top_module (
  input  wire        clk,
  input  wire        rst_n,
  input  wire        init_start,
  input  wire        partner_req,
  input  wire        partner_ack,
  input  wire        train_pattern_ok,
  input  wire        error_detected,
  output reg         link_req_out,
  output reg         link_ack_out,
  output wire        link_active,
  output wire        link_error,
  output reg  [2:0]  state_out
);

  localparam ST_RESET    = 3'd0;
  localparam ST_REQ      = 3'd1;
  localparam ST_TRAIN    = 3'd2;
  localparam ST_CONFIG   = 3'd3;
  localparam ST_ACTIVE   = 3'd4;
  localparam ST_ERROR    = 3'd5;
  localparam ST_RECOVERY = 3'd6;

  reg [3:0] timeout_cnt;

  assign link_active = (state_out == ST_ACTIVE);
  assign link_error  = (state_out == ST_ERROR);

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      state_out    <= ST_RESET;
      link_req_out <= 1'b0;
      link_ack_out <= 1'b0;
      timeout_cnt  <= 4'd0;
    end else begin
      case (state_out)
        ST_RESET: begin
          link_req_out <= 1'b0;
          link_ack_out <= 1'b0;
          timeout_cnt  <= 4'd0;
          if (init_start) begin
            state_out    <= ST_REQ;
            link_req_out <= 1'b1;
          end
        end

        ST_REQ: begin
          link_req_out <= 1'b1;
          if (partner_ack) begin
            state_out    <= ST_TRAIN;
            link_ack_out <= 1'b1;
            timeout_cnt  <= 4'd0;
          end
        end

        ST_TRAIN: begin
          if (train_pattern_ok) begin
            state_out   <= ST_CONFIG;
            timeout_cnt <= 4'd0;
          end else if (timeout_cnt >= 4'd7) begin
            state_out   <= ST_ERROR;
            timeout_cnt <= 4'd0;
          end else begin
            timeout_cnt <= timeout_cnt + 4'd1;
          end
        end

        ST_CONFIG: begin
          link_ack_out <= 1'b1;
          if (partner_req) begin
            state_out <= ST_ACTIVE;
          end
        end

        ST_ACTIVE: begin
          link_req_out <= 1'b1;
          link_ack_out <= 1'b1;
          if (error_detected) begin
            state_out <= ST_ERROR;
          end
        end

        ST_ERROR: begin
          link_req_out <= 1'b0;
          link_ack_out <= 1'b0;
          state_out    <= ST_RECOVERY;
        end

        ST_RECOVERY: begin
          state_out    <= ST_REQ;
          link_req_out <= 1'b1;
        end

        default: state_out <= ST_RESET;
      endcase
    end
  end

endmodule
Verilog-2001 / SV Saved
Font: |
Open Simulation Lab
// Click Run Tests (or press Ctrl+Enter) to compile your RTL and simulate against hidden testbenches.
Simulation Timing Diagram (VCD Waveform)
100%
No simulation waveform yet. Run tests to simulate and generate VCD traces.
No compilation run yet. Syntax warnings and elaboration messages will appear here.
No simulation output yet. Raw stdout from vvp will appear here.

RTL Problems / Level 6 · Advanced RTL & Protocol Design

What You Will Learn

By solving Educational Chiplet Link Initialization & Sideband Training FSM, you will acquire core industry skills:

  • Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
  • Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
  • Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
  • Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Design an educational link-training finite state machine inspired by UCIe sideband handshaking, link configuration, and error recovery.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Objective: Implement a 7-state chiplet link initialization controller: RESET, INIT_REQ, LINK_TRAIN, CONFIG, ACTIVE, ERROR, and RECOVERY. Coordinate bidirectional handshaking with a partner die (partner_req, partner_ack, train_done), monitor link timeouts, and support fault recovery without full system reset.

Prerequisites: UCIe / PCIe link training concepts, sideband state machines, timeout monitoring, hardware fault recovery.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

PortDirWidthDescription
clk, rst_ninput1Clock and active-low synchronous reset
init_startinput1Host processor command to bring up chiplet link
partner_req, partner_ackinput1Handshake signals received from opposite die
train_pattern_okinput1PHY signal indicating PRBS bit-lock achieved
error_detectedinput1Parity/CRC fault trigger
link_req_out, link_ack_outoutput1Handshake signals transmitted to opposite die
link_active, link_erroroutput1Status flags for active transmission and error
state_out[2:0]output3Current FSM state: 0=RESET, 1=REQ, 2=TRAIN, 3=CFG, 4=ACTIVE, 5=ERR, 6=RECOVERY

Timing Constraints & Synthesizable RTL Rules

⚡ Synthesizable Implementation Guidelines

Timing Contract: Clocked on posedge clk with active-low rst_n. Timeout counter fires after 8 consecutive cycles stuck in LINK_TRAIN without partner response.

Synthesis Constraints: Clear educational protocol abstraction. Synthesizable Verilog-2001.

Architectural Deep Dive & Implementation Walkthrough

UCIe and Multi-Die Link Bring-Up

Modern advanced packaging (TSMC CoWoS, Intel EMIB) connects multiple silicon dies through micro-bumps. Before high-speed main data lanes (32 Gbps+) can transmit, a low-speed Sideband Channel brings up and trains the interface.

Educational State Machine Overview

  • Phase 1: Discovery (REQ / ACK): Dies signal presence across dedicated sideband wires.
  • Phase 2: PHY Training: Pseudorandom bit sequences (PRBS) calibrate receiver equalizers and per-lane delay locks.
  • Phase 3: Parameter Configuration: Negotiate lane count, clock frequency, and CRC algorithms.
  • Phase 4: Active Operation & Recovery: Upon parity fault or signal loss, the controller enters RECOVERY to re-lock PHY equalizers without resetting the host CPU.

Note: This module implements an educational abstraction of multi-die link training principles; actual UCIe specifications define detailed sub-states for lane repair and power management.

Common RTL Designer Pitfalls

⚠️ Common Mistakes to Avoid

Staying in ST_TRAIN forever without a timeout mechanism, which locks up the chip if partner die fails to power up.

Silicon & Hardware Engineering Notes

🛠️ ASIC vs FPGA Hardware Considerations

Universal Chiplet Interconnect Express (UCIe) incorporates redundant spare micro-bumps per cluster that are dynamically swapped in during the training phase if physical faults are detected.

Starter RTL Code

module top_module (
  input  wire        clk,
  input  wire        rst_n,
  input  wire        init_start,
  input  wire        partner_req,
  input  wire        partner_ack,
  input  wire        train_pattern_ok,
  input  wire        error_detected,
  output reg         link_req_out,
  output reg         link_ack_out,
  output wire        link_active,
  output wire        link_error,
  output reg  [2:0]  state_out
);

  // States:
  // 3'd0: ST_RESET   - wait for init_start
  // 3'd1: ST_REQ     - send link_req_out, wait for partner_ack

Verified Reference Solution

🔒 Reveal Verified Reference RTL Solution
module top_module (
  input  wire        clk,
  input  wire        rst_n,
  input  wire        init_start,
  input  wire        partner_req,
  input  wire        partner_ack,
  input  wire        train_pattern_ok,
  input  wire        error_detected,
  output reg         link_req_out,
  output reg         link_ack_out,
  output wire        link_active,
  output wire        link_error,
  output reg  [2:0]  state_out
);

  localparam ST_RESET    = 3'd0;
  localparam ST_REQ      = 3'd1;
  localparam ST_TRAIN    = 3'd2;
  localparam ST_CONFIG   = 3'd3;
  localparam ST_ACTIVE   = 3'd4;
  localparam ST_ERROR    = 3'd5;
  localparam ST_RECOVERY = 3'd6;

  reg [3:0] timeout_cnt;

  assign link_active = (state_out == ST_ACTIVE);
  assign link_error  = (state_out == ST_ERROR);

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      state_out    <= ST_RESET;
      link_req_out <= 1'b0;
      link_ack_out <= 1'b0;
      timeout_cnt  <= 4'd0;
    end else begin
      case (state_out)
        ST_RESET: begin
          link_req_out <= 1'b0;
          link_ack_out <= 1'b0;
          timeout_cnt  <= 4'd0;
          if (init_start) begin
            state_out    <= ST_REQ;
            link_req_out <= 1'b1;
          end
        end

        ST_REQ: begin
          link_req_out <= 1'b1;
          if (partner_ack) begin
            state_out    <= ST_TRAIN;
            link_ack_out <= 1'b1;
            timeout_cnt  <= 4'd0;
          end
        end

        ST_TRAIN: begin
          if (train_pattern_ok) begin
            state_out   <= ST_CONFIG;
            timeout_cnt <= 4'd0;
          end else if (timeout_cnt >= 4'd7) begin
            state_out   <= ST_ERROR;
            timeout_cnt <= 4'd0;
          end else begin
            timeout_cnt <= timeout_cnt + 4'd1;
          end
        end

        ST_CONFIG: begin
          link_ack_out <= 1'b1;
          if (partner_req) begin
            state_out <= ST_ACTIVE;
          end
        end

        ST_ACTIVE: begin
          link_req_out <= 1'b1;
          link_ack_out <= 1'b1;
          if (error_detected) begin
            state_out <= ST_ERROR;
          end
        end

        ST_ERROR: begin
          link_req_out <= 1'b0;
          link_ack_out <= 1'b0;
          state_out    <= ST_RECOVERY;
        end

        ST_RECOVERY: begin
          state_out    <= ST_REQ;
          link_req_out <= 1'b1;
        end

        default: state_out <= ST_RESET;
      endcase
    end
  end

endmodule

Related RTL Problems in Level 6

  • Manchester Encoder — Combine a data bit with the clock to produce a Manchester-encoded line signal — the self-clocking encoding used in classic Ethernet and RFID.
  • Manchester Decoder — Recover the original data bit from a Manchester-encoded line signal — the exact inverse of the Manchester Encoder problem.
  • Quadrature Rotary Encoder Decoder — Decode the two-phase A/B signal from a real rotary knob or mouse wheel into a direction and position count — sample B on every rising edge of A.

Connected EcrioniX Learning Resources

Accelerate your VLSI engineering knowledge with these curated learning materials:

Dedicated Learning Roadmap
Advanced SoC and Chiplet RTL Roadmap →

Progress through step-by-step verified modules from fundamentals to advanced silicon design.

Knowledge Diagnostic
RTL Skill Assessment (10-30m) →

Benchmark your hardware knowledge across 10 semiconductor domains and receive study roadmaps.

In-Depth Theory Guide
UCIe & Chiplet Interconnect Architecture →

Explore foundational circuit theory, waveform timing, and physical hardware implementation.

Frequently Asked Questions

What does Educational Chiplet Link Initialization & Sideband Training FSM require?

Design an educational link-training finite state machine inspired by UCIe sideband handshaking, link configuration, and error recovery. Implement it as Verilog module top_module matching the listed ports.

Is this design combinational or sequential?

Tags: advanced-rtl, ucie-and-chiplet-architecture, systemverilog, asic, fpga. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.

How is my solution graded?

A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.

How does this challenge help with semiconductor interviews?

Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of Educational Chiplet Link Initialization & Sideband Training FSM to assess real-world synthesizability and race-condition awareness.