CRC-4 Generator

Verilog problems / Combinational Design

What you must build

Compute the 4-bit CRC remainder of an 8-bit message using the CRC-4 (poly x⁴+x+1) bit-serial algorithm, entirely in combinational logic.

Engineers use “CRC-4 Generator” as a building block in combinational design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  [7:0] data,
  output [3:0] crc
);

  // Your code here — bit-serial CRC-4 (poly x^4+x+1): fb=crc[3]^bit; crc<<=1; if(fb) crc^=4'b0011.

endmodule

Why this shows up in interviews

CRC-4 Generator sits under Combinational Design (combinational, protocol). Concept: A CRC is the remainder of polynomial division. The classic bit-serial method processes one message bit at a time, MSB first: feed back fb = crc[3] ^ bit , shift the register left, and if fb was set, XOR in the generator polynomial's low bits ( 4'b0011 for x⁴+x+1). Unrolling this loop over all 8 input bits in an always @* block (or a function) gives a pure-combinational CRC generator — get the polynomial constant wrong and every non-trivial input produces a silently corrupted checksum.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• 2-to-1 Multiplexer — Select between two 1-bit inputs using sel. When sel=0 output a; when sel=1 output b.
• 1-Bit Full Adder — Compute sum and carry-out for a + b + cin.
• 4-to-1 Multiplexer — Select one of four 1-bit inputs using a 2-bit sel. sel=00→in0, 01→in1, 10→in2, 11→in3.
• 4-to-2 Priority Encoder — Output the index of the highest-priority (MSB-most) set bit in a 4-bit input, plus a valid flag when any bit is set.

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