Credit-Based Flow Control Controller for Inter-Chiplet Links

RTL Problems / Level 6 · Advanced RTL & Protocol Design

What You Will Learn

By solving Credit-Based Flow Control Controller for Inter-Chiplet Links, you will acquire core industry skills:

• Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
• Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
• Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
• Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Design a credit-based flow control transmit manager for high-speed chiplet and PCIe/UCIe links with zero-credit stalling and underflow protection.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

Timing Constraints & Synthesizable RTL Rules

Architectural Deep Dive & Implementation Walkthrough

Common RTL Designer Pitfalls

Silicon & Hardware Engineering Notes

Starter RTL Code

module top_module (
  input  wire        clk,
  input  wire        rst_n,
  input  wire        tx_valid,
  input  wire [31:0] tx_data,
  output wire        tx_ready,
  output reg         phy_tx_valid,
  output reg  [31:0] phy_tx_data,
  input  wire        credit_return_in,
  output reg  [3:0]  credits_available
);

  // Implement credit-based flow control:
  // 1. Reset value of credits_available = 4'd8.
  // 2. tx_ready = (credits_available > 0).
  // 3. When tx_valid && tx_ready: transmit data (phy_tx_valid=1) and decrement credit.
  // 4. When credit_return_in: increment credit.
  // 5. Handle simultaneous send and credit return without count jitter or underflow.

Verified Reference Solution

module top_module (
  input  wire        clk,
  input  wire        rst_n,
  input  wire        tx_valid,
  input  wire [31:0] tx_data,
  output wire        tx_ready,
  output reg         phy_tx_valid,
  output reg  [31:0] phy_tx_data,
  input  wire        credit_return_in,
  output reg  [3:0]  credits_available
);

  assign tx_ready = (credits_available > 4'd0);
  wire send_beat = tx_valid && tx_ready;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      credits_available <= 4'd8;
      phy_tx_valid      <= 1'b0;
      phy_tx_data       <= 32'h0;
    end else begin
      phy_tx_valid <= send_beat;
      if (send_beat) begin
        phy_tx_data <= tx_data;
      end

      case ({send_beat, credit_return_in})
        2'b10: begin // Sent, no return -> decrement
          if (credits_available > 4'd0)
            credits_available <= credits_available - 4'd1;
        end
        2'b01: begin // No send, return -> increment
          if (credits_available < 4'd15)
            credits_available <= credits_available + 4'd1;
        end
        2'b11: begin // Simultaneous send and return -> net zero change
          credits_available <= credits_available;
        end
        default: ; // 2'b00 -> hold
      endcase
    end
  end

endmodule

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Frequently Asked Questions