Chiplet Ingress Buffer Credit Return Manager

RTL Problems / Level 6 · Advanced RTL & Protocol Design

What You Will Learn

By solving Chiplet Ingress Buffer Credit Return Manager, you will acquire core industry skills:

• Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
• Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
• Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
• Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Design a receiver-side credit return accumulator that batches freed buffer credits to optimize sideband bandwidth in chiplet interfaces.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

Timing Constraints & Synthesizable RTL Rules

Architectural Deep Dive & Implementation Walkthrough

Common RTL Designer Pitfalls

Silicon & Hardware Engineering Notes

Starter RTL Code

module top_module (
  input  wire        clk,
  input  wire        rst_n,
  input  wire        buf_release,
  input  wire [2:0]  return_threshold,
  output reg         credit_return_strobe,
  output reg  [2:0]  credits_to_return,
  output reg  [3:0]  pending_credits
);

  // Implement credit return manager:
  // 1. Accumulate buf_release events into pending_credits.
  // 2. When pending_credits >= return_threshold OR (pending_credits > 0 and idle for 8 cycles):
  //    Assert credit_return_strobe = 1, credits_to_return = pending_credits, and clear pending_credits.

endmodule

Verified Reference Solution

module top_module (
  input  wire        clk,
  input  wire        rst_n,
  input  wire        buf_release,
  input  wire [2:0]  return_threshold,
  output reg         credit_return_strobe,
  output reg  [2:0]  credits_to_return,
  output reg  [3:0]  pending_credits
);

  reg [3:0] flush_timer;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      credit_return_strobe <= 1'b0;
      credits_to_return    <= 3'd0;
      pending_credits      <= 4'd0;
      flush_timer          <= 4'd0;
    end else begin
      credit_return_strobe <= 1'b0;
      credits_to_return    <= 3'd0;

      // Calculate next unreturned credits
      if (credit_return_strobe) begin
        // Flush occurred on previous cycle: start fresh or add new incoming release
        if (buf_release) begin
          pending_credits <= 4'd1;
          flush_timer     <= 4'd0;
        end else begin
          pending_credits <= 4'd0;
          flush_timer     <= 4'd0;
        end
      end else begin
        if (buf_release) begin
          flush_timer <= 4'd0;
          if ((pending_credits + 4'd1) >= {1'b0, return_threshold}) begin
            credit_return_strobe <= 1'b1;
            credits_to_return    <= (pending_credits + 4'd1);
            pending_credits      <= 4'd0;
          end else begin
            pending_credits <= pending_credits + 4'd1;
          end
        end else if (pending_credits > 4'd0) begin
          if (flush_timer >= 4'd7) begin // 8 cycles of idle flush
            credit_return_strobe <= 1'b1;
            credits_to_return    <= pending_credits[2:0];
            pending_credits      <= 4'd0;
            flush_timer          <= 4'd0;
          end else begin
            flush_timer <= flush_timer + 4'd1;
          end
        end else begin
          flush_timer <= 4'd0;
        end
      end
    end
  end

endmodule

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• Manchester Decoder — Recover the original data bit from a Manchester-encoded line signal — the exact inverse of the Manchester Encoder problem.
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Frequently Asked Questions