Chiplet Flit-to-Stream Elastic Protocol Bridge

RTL Problems / Level 6 · Advanced RTL & Protocol Design

What You Will Learn

By solving Chiplet Flit-to-Stream Elastic Protocol Bridge, you will acquire core industry skills:

• Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
• Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
• Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
• Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Design an elastic streaming protocol bridge with 4-entry FIFO buffering, cut-through routing, and lossless backpressure.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

Timing Constraints & Synthesizable RTL Rules

Architectural Deep Dive & Implementation Walkthrough

Common RTL Designer Pitfalls

Silicon & Hardware Engineering Notes

Starter RTL Code

module top_module (
  input  wire        clk,
  input  wire        rst_n,
  input  wire        s_valid,
  output wire        s_ready,
  input  wire [63:0] s_data,
  input  wire        s_last,
  output wire        m_valid,
  input  wire        m_ready,
  output wire [63:0] m_data,
  output wire        m_last,
  output reg  [2:0]  buffer_occupancy
);

  // Implement a 4-deep elastic streaming bridge:
  // 1. Buffer storage for 4 x (64-bit data + 1-bit last).
  // 2. s_ready = (buffer_occupancy < 3'd4).
  // 3. m_valid = (buffer_occupancy > 3'd0).

Verified Reference Solution

module top_module (
  input  wire        clk,
  input  wire        rst_n,
  input  wire        s_valid,
  output wire        s_ready,
  input  wire [63:0] s_data,
  input  wire        s_last,
  output wire        m_valid,
  input  wire        m_ready,
  output wire [63:0] m_data,
  output wire        m_last,
  output reg  [2:0]  buffer_occupancy
);

  reg [64:0] mem [0:3];
  reg [1:0] wr_ptr, rd_ptr;

  assign s_ready = (buffer_occupancy < 3'd4);
  assign m_valid = (buffer_occupancy > 3'd0);

  wire [64:0] rd_entry = mem[rd_ptr];
  assign m_data = rd_entry[63:0];
  assign m_last = rd_entry[64];

  wire push = s_valid && s_ready;
  wire pop  = m_valid && m_ready;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      wr_ptr           <= 2'd0;
      rd_ptr           <= 2'd0;
      buffer_occupancy <= 3'd0;
    end else begin
      if (push) begin
        mem[wr_ptr] <= {s_last, s_data};
        wr_ptr      <= wr_ptr + 2'd1;
      end

      if (pop) begin
        rd_ptr <= rd_ptr + 2'd1;
      end

      case ({push, pop})
        2'b10: buffer_occupancy <= buffer_occupancy + 3'd1;
        2'b01: buffer_occupancy <= buffer_occupancy - 3'd1;
        default: ; // 2'b00 or 2'b11 -> unchanged
      endcase
    end
  end

endmodule

Related RTL Problems in Level 6

• Manchester Encoder — Combine a data bit with the clock to produce a Manchester-encoded line signal — the self-clocking encoding used in classic Ethernet and RFID.
• Manchester Decoder — Recover the original data bit from a Manchester-encoded line signal — the exact inverse of the Manchester Encoder problem.
• Quadrature Rotary Encoder Decoder — Decode the two-phase A/B signal from a real rotary knob or mouse wheel into a direction and position count — sample B on every rising edge of A.

Frequently Asked Questions