AHB – Advanced High-performance Bus

Overview & Pipeline

The key performance advantage of AHB over APB is its two-stage pipeline. While the data phase of one transfer is in progress, the address phase of the next transfer is already being presented. This keeps the bus active every cycle rather than spending idle cycles re-presenting addresses.

Because address and data overlap, a slave must register the address signals on the cycle they appear (the address phase) and use them during the following cycle (the data phase) when HWDATA or HRDATA is valid.

Signal Reference

HTRANS — Transfer Types

HTRANS tells the slave what kind of transfer is currently on the address bus.

HBURST — Burst Types

WRAP bursts are used for cache-line fills: the processor requests the critical word first, then the burst wraps around the cache-line boundary so all words are fetched in the minimum number of cycles. INCR bursts are general-purpose sequential accesses with no boundary constraint.

Write Transfer Timing

A 3-beat INCR3 write burst. The address of beat N+1 appears on the bus during the data phase of beat N.

Read Transfer Timing

For a read, the slave presents HRDATA during the data phase. The master samples HRDATA on the rising edge when HREADY is HIGH.

Wait States (HREADY)

A slave extends its data phase by driving HREADYOUT LOW. The bus multiplexer propagates this as HREADY LOW to the master. The master must hold all address-phase signals stable (HADDR, HTRANS, HWRITE, HSIZE, HBURST) and not advance to the next transfer until HREADY returns HIGH.

Multiple wait states can be inserted by keeping HREADY LOW for additional cycles. There is no protocol-defined maximum, but practical designs limit wait states to avoid starving other masters.

HRESP — Response Codes

AHB vs AHB-Lite

AHB-Lite (defined in AMBA 3) is a single-master subset of full AHB. It removes the arbiter, multi-master bus grant signals, and RETRY/SPLIT responses. It is the version used in the vast majority of modern Cortex-M based SoCs because most embedded designs have a single bus master (the CPU) plus a DMA controller that can be handled separately.

Verilog RTL — AHB-Lite Slave (Register File)

A minimal AHB-Lite slave with a 4×32-bit register file. The key detail is latching address-phase signals at the end of the address phase so they are available during the data phase.

module ahb_lite_slave (
  input  wire        HCLK,
  input  wire        HRESETn,

  // Address phase inputs (registered on rising edge when HREADY=1)
  input  wire        HSEL,
  input  wire [31:0] HADDR,
  input  wire        HWRITE,
  input  wire [1:0]  HTRANS,
  input  wire [2:0]  HSIZE,
  input  wire        HREADY,     // bus HREADY in

  // Data phase
  input  wire [31:0] HWDATA,
  output reg  [31:0] HRDATA,
  output wire        HREADYOUT,  // slave ready (1 = no wait)
  output wire        HRESP       // 0=OKAY 1=ERROR (AHB-Lite)
);

  // Always ready, always OKAY for this simple slave
  assign HREADYOUT = 1'b1;
  assign HRESP     = 1'b0;

  // Latch address-phase signals at end of address phase
  reg        lat_sel, lat_write;
  reg [31:0] lat_addr;
  reg [1:0]  lat_trans;

  always @(posedge HCLK) begin
    if (!HRESETn) begin
      lat_sel   <= 1'b0;
      lat_write <= 1'b0;
      lat_addr  <= 32'h0;
      lat_trans <= 2'b00;
    end else if (HREADY) begin   // sample only when bus is free
      lat_sel   <= HSEL;
      lat_write <= HWRITE;
      lat_addr  <= HADDR;
      lat_trans <= HTRANS;
    end
  end

  // 4-register file
  reg [31:0] regs [0:3];
  wire [1:0] reg_idx = lat_addr[3:2];
  wire       valid   = lat_sel && (lat_trans[1] == 1'b1); // NONSEQ or SEQ

  // Write — data phase
  integer i;
  always @(posedge HCLK) begin
    if (!HRESETn) begin
      for (i = 0; i < 4; i = i + 1) regs[i] <= 32'h0;
    end else if (valid && lat_write && HREADY)
      regs[reg_idx] <= HWDATA;
  end

  // Read — combinational
  always @(*) begin
    if (valid && !lat_write)
      HRDATA = regs[reg_idx];
    else
      HRDATA = 32'h0;
  end

endmodule

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