On-Chip Communication

Hardware Protocols

Learn AMBA bus protocols — signal definitions, timing diagrams, state machines, and RTL implementation for APB, AHB, and AXI.

AMBA Family

Protocol Articles

From low-bandwidth peripheral buses to high-speed interconnects.

APB – Advanced Peripheral Bus

Low-bandwidth, low-power bus for peripheral access. Covers signals, IDLE/SETUP/ACCESS state machine, write/read transfers, PREADY wait states, PSLVERR, and RTL implementation.

CXS – CCIX Transport Interface

Flit-based AMBA link interface for cache-coherent CPU–accelerator communication. Covers signals, flit structure, link activation, credit-based flow control, and RTL implementation.

AXI4 – Advanced eXtensible Interface

High-performance protocol with 5 independent channels, out-of-order transactions, and burst support up to 256 beats. Covers handshake, write/read timing, burst types, response codes, and AXI4-Lite RTL.

Unidirectional streaming interface with no address channel. Covers TDATA/TVALID/TREADY handshake, TLAST packet framing, TKEEP byte qualifiers, backpressure, skid buffer RTL, and use cases in DSP, video, and networking.