APB — Advanced Peripheral Bus

1. Where APB Fits in AMBA

AMBA (Advanced Microcontroller Bus Architecture) is ARM's open on-chip bus specification. It defines a hierarchy of protocols suited to different bandwidth and latency requirements:

APB is always a slave-only bus — it hangs off an AHB-to-APB or AXI-to-APB bridge. The bridge converts high-speed bus accesses into APB transactions.

2. APB Signal Definition

All signals are driven by the master (bridge) except PRDATA, PREADY, and PSLVERR which are driven by the slave.

3. APB State Machine

The APB master operates a simple 3-state FSM. Every transfer takes a minimum of 2 clock cycles.

• IDLE — default state. No transfer in progress. PSEL = 0
• SETUP — master asserts PSEL, drives PADDR, PWRITE, PWDATA. PENABLE = 0
• ACCESS — master asserts PENABLE. Slave drives PRDATA/PREADY. Transfer completes when PREADY = 1

4. Write Transfer

No Wait States (minimum 2 cycles)

• T2 (SETUP): Master asserts PSEL, drives PADDR, PWRITE=1, PWDATA. PENABLE=0
• T3 (ACCESS): Master asserts PENABLE=1. Slave responds with PREADY=1 — write data sampled, transfer complete
• After T3: master deasserts PSEL and PENABLE, returns to IDLE

5. Read Transfer

• T2 (SETUP): Master drives PADDR, PWRITE=0, asserts PSEL
• T3 (ACCESS): PENABLE=1. Slave places read data on PRDATA and asserts PREADY=1
• Master samples PRDATA at the rising edge of T3 when PREADY=1

6. Wait States — PREADY

A slow slave drives PREADY=0 in the ACCESS phase to insert wait states. The bus master holds all signals stable until the slave is ready.

7. Error Response — PSLVERR

Introduced in APB3. Slave asserts PSLVERR=1 in the same cycle as PREADY=1 to signal a failed transfer (e.g., invalid address, write to read-only register).

8. Verilog RTL Implementation

APB Slave — Register File (4 × 32-bit registers)

module apb_slave #(
  parameter DATA_W = 32,
  parameter ADDR_W = 32
)(
  input  wire              PCLK,
  input  wire              PRESETn,
  input  wire [ADDR_W-1:0] PADDR,
  input  wire              PSEL,
  input  wire              PENABLE,
  input  wire              PWRITE,
  input  wire [DATA_W-1:0] PWDATA,
  output reg  [DATA_W-1:0] PRDATA,
  output wire              PREADY,
  output wire              PSLVERR
);
  // 4 internal 32-bit registers at offsets 0x00, 0x04, 0x08, 0x0C
  reg [DATA_W-1:0] regs[0:3];

  // No wait states, no errors
  assign PREADY  = 1'b1;
  assign PSLVERR = 1'b0;

  // Write — sample on ACCESS phase
  always @(posedge PCLK or negedge PRESETn) begin
    if (!PRESETn) begin
      regs[0] <= 0; regs[1] <= 0;
      regs[2] <= 0; regs[3] <= 0;
    end else if (PSEL && PENABLE && PWRITE && PREADY) begin
      regs[PADDR[3:2]] <= PWDATA;
    end
  end

  // Read — combinational in SETUP / ACCESS
  always @(*) begin
    if (PSEL && !PWRITE)
      PRDATA = regs[PADDR[3:2]];
    else
      PRDATA = 32'h0;
  end

endmodule

APB Master (Simple — for testbench)

// APB write task
task apb_write;
  input [31:0] addr, data;
  begin
    @(posedge PCLK);
    // SETUP phase
    PADDR   <= addr;
    PWRITE  <= 1'b1;
    PWDATA  <= data;
    PSEL    <= 1'b1;
    PENABLE <= 1'b0;
    @(posedge PCLK);
    // ACCESS phase
    PENABLE <= 1'b1;
    @(posedge PCLK);
    while (!PREADY) @(posedge PCLK); // wait
    // End transfer
    PSEL    <= 1'b0;
    PENABLE <= 1'b0;
  end
endtask

// APB read task
task apb_read;
  input  [31:0] addr;
  output [31:0] data;
  begin
    @(posedge PCLK);
    PADDR   <= addr;
    PWRITE  <= 1'b0;
    PSEL    <= 1'b1;
    PENABLE <= 1'b0;
    @(posedge PCLK);
    PENABLE <= 1'b1;
    @(posedge PCLK);
    while (!PREADY) @(posedge PCLK);
    data    = PRDATA;
    PSEL    <= 1'b0;
    PENABLE <= 1'b0;
  end
endtask

9. Where APB Is Used

10. Interview Questions

Q: What is the minimum number of cycles for an APB transfer?

2 cycles — one SETUP cycle and one ACCESS cycle (assuming PREADY=1 with no wait states).

Q: When is PENABLE asserted?

In the second cycle of the transfer (ACCESS phase). It is LOW during SETUP and HIGH during ACCESS.

Q: Can PADDR or PWDATA change during a transfer?

No. All master-driven signals must remain stable from SETUP through the end of ACCESS (when PREADY=1).

Q: What happens if PREADY stays LOW forever?

The bus stalls indefinitely. In real designs, a watchdog or timeout mechanism at the bridge detects this and generates an error response.

Q: Difference between APB2, APB3, and APB4?

• APB2 — basic signals: PCLK, PRESETn, PADDR, PSEL, PENABLE, PWRITE, PWDATA, PRDATA
• APB3 — added PREADY (wait states) and PSLVERR (error response)
• APB4 — added PSTRB (byte strobes) and PPROT (protection)

Q: Can APB have multiple masters?

No. APB is a single-master bus. The AHB-to-APB or AXI-to-APB bridge acts as the sole master. Multiple AHB/AXI masters access APB only through the bridge.

11. APB in Real SoC Design — Practical Considerations

APB Register Map Design

In practice, the most important design decision for an APB slave is the register map — how PADDR values map to internal configuration and status registers. A well-designed register map groups related controls together at aligned addresses, separates read-only status from read-write control, and leaves address gaps for future expansion. By convention, each register occupies 4 bytes (word-aligned), so PADDR[1:0] is typically ignored. The APB slave decodes PADDR[N:2] where N is the number of address bits needed to cover all registers.

A common pitfall is designing a register map with write-only registers (registers that can be written but where reading returns 0). While technically valid in the APB spec, write-only registers complicate software driver development because the CPU cannot read-back the current value to perform read-modify-write operations. Prefer registers that return their last written value on reads — this is called "read-back support" and is a strong design recommendation for all control registers.

Timing Constraints for APB

APB operates synchronously to PCLK. Because APB is a low-bandwidth peripheral bus, PCLK is typically derived from a divided-down version of the main system clock. A 1 GHz SoC might run AXI4 at 1 GHz, AHB at 500 MHz, and APB at 100–250 MHz. This means the APB bridge contains a clock domain crossing: the AHB or AXI side runs at high frequency, and the APB side at a lower frequency. The bridge must synchronize control signals across this boundary, adding latency to each APB transfer. This latency is acceptable because APB is only used for peripheral register accesses where timing is not critical.

STA (Static Timing Analysis) for APB slaves is straightforward compared to AXI4: all paths are synchronous to one clock (PCLK), there is no pipelining, and the maximum combinational depth is typically 2–3 gates (address decode + mux). The main timing concern is PREADY — if PREADY is generated combinationally from a memory or state machine, it must meet the setup time requirement of the master's PCLK edge. Most designers register PREADY to avoid this combinational path.

APB in Power-Managed SoCs

APB's simple, synchronous architecture makes it particularly well-suited for power-managed designs. Because APB has no pipeline and no outstanding transactions, the APB slave can be placed in a power island that is fully shut down when unused. The AHB-to-APB bridge simply stalls (holds PREADY low or asserts PSLVERR) if the APB domain is powered off. When the software driver needs to access the peripheral, it wakes the power domain, waits for the wake-up time (typically microseconds), and then proceeds with APB transfers. This coarse-grained power management is used extensively in mobile SoCs for peripherals like Bluetooth controllers, camera interfaces, and audio codecs.

Verifying APB Compliance

A complete APB verification environment checks the following properties: the slave never asserts PSLVERR without PREADY being simultaneously high; PRDATA is stable before PREADY goes high; the slave holds PREADY low for the correct number of wait states; PADDR, PWRITE, and PWDATA are stable throughout the SETUP and ACCESS phases; PSELx is not deasserted before PREADY; and the slave correctly resets all registers to their default values on PRESETn. A UVM-based APB VIP (Verification IP) generates constrained-random traffic and checks these properties using assertions. For most VLSI interview scenarios, demonstrating knowledge of these protocol rules — not just the waveform diagrams — separates candidates who understand the protocol from those who have memorized the timing diagram.