AXI4-Stream – AMBA Streaming Interface

Overview & Comparison

AXI4 (full) is designed for memory-mapped transactions — each transfer has an address, allowing random access to any location. AXI4-Stream removes the address dimension completely. Data simply flows from producer to consumer in the order it is presented, with no concept of memory location.

This simplicity is its strength: there is only one channel with a handful of signals, yet it can sustain 100% bus utilisation (one data beat every clock cycle) when the slave keeps TREADY asserted. It is the dominant interface inside Xilinx/AMD and Intel/Altera FPGA IP cores, Arm Cortex-A DMA engines, and all modern video/image signal processing pipelines.

Signal Reference

Only TDATA, TVALID, and TREADY are mandatory. All other signals are optional and included only when the application needs them.

TVALID / TREADY Handshake

The handshake rule is identical to AXI4: a transfer occurs on the rising clock edge when both TVALID and TREADY are HIGH.

When the slave de-asserts TREADY (stall), the master must hold TDATA and TVALID stable until TREADY returns. This is called backpressure — the slave is telling the master it is not ready to consume data.

Packet Framing with TLAST

AXI4-Stream itself has no concept of a packet size — data beats flow continuously. TLAST provides a single-bit end-of-packet marker: when HIGH on a data beat, it signals that this is the last beat of the current packet or frame. The slave resets its framing state after the TLAST beat.

Two back-to-back packets can be transferred without any idle cycle between them — the cycle after TLAST simply carries the first beat of the next packet.

TKEEP & TSTRB — Byte Qualifiers

When the final beat of a packet does not fill the entire data bus (e.g., a 10-byte payload on a 32-bit / 4-byte bus), TKEEP marks which byte lanes carry meaningful data.

Backpressure

Backpressure is the mechanism by which a slow slave signals the master to pause. When the slave de-asserts TREADY=0, no transfer occurs even if TVALID is HIGH. The master must hold its data stable on TDATA (along with TVALID and all sideband signals) until TREADY returns.

A common pattern is to insert a skid buffer (a two-entry register FIFO) between the master and slave. This absorbs one beat of backpressure without stalling the master, improving pipeline efficiency.

Verilog RTL

Two complementary modules: an AXI4-Stream master that generates a packet, and a skid-buffer slave that absorbs one cycle of backpressure.

module axis_master #(
  parameter DW        = 32,
  parameter PKT_BEATS = 4   // beats per packet
) (
  input  wire          aclk,
  input  wire          aresetn,

  // AXI4-Stream master output
  output reg  [DW-1:0] m_tdata,
  output reg           m_tvalid,
  output reg           m_tlast,
  output wire [DW/8-1:0] m_tkeep,
  input  wire          m_tready,

  // trigger to start sending one packet
  input  wire          send
);

  reg [$clog2(PKT_BEATS):0] beat_cnt;
  assign m_tkeep = {(DW/8){1'b1}};  // all bytes valid

  always @(posedge aclk) begin
    if (!aresetn) begin
      m_tvalid <= 1'b0; m_tlast <= 1'b0;
      m_tdata  <= '0;  beat_cnt <= 0;
    end else begin
      if (send && !m_tvalid) begin
        m_tvalid <= 1'b1;
        m_tdata  <= 32'hA000_0000;
        beat_cnt <= 1;
        m_tlast  <= (PKT_BEATS == 1);
      end else if (m_tvalid && m_tready) begin
        if (m_tlast) begin  // packet done
          m_tvalid <= 1'b0;
          m_tlast  <= 1'b0;
          beat_cnt <= 0;
        end else begin
          beat_cnt <= beat_cnt + 1;
          m_tdata  <= m_tdata + 1;
          m_tlast  <= (beat_cnt + 1 == PKT_BEATS - 1);
        end
      end
    end
  end
endmodule

// Skid buffer: absorbs one beat of backpressure so the upstream
// master never stalls even when downstream de-asserts TREADY.
module axis_skid_buf #(parameter DW = 32) (
  input  wire          aclk, aresetn,

  input  wire [DW-1:0] s_tdata,
  input  wire          s_tvalid, s_tlast,
  output reg           s_tready,

  output reg  [DW-1:0] m_tdata,
  output reg           m_tvalid, m_tlast,
  input  wire          m_tready
);

  reg [DW-1:0] skid_data;
  reg          skid_valid, skid_last;

  always @(posedge aclk) begin
    if (!aresetn) begin
      m_tvalid <= 1'b0; skid_valid <= 1'b0; s_tready <= 1'b1;
    end else begin
      if (m_tready || !m_tvalid) begin
        if (skid_valid) begin          // drain skid slot first
          m_tdata  <= skid_data;
          m_tlast  <= skid_last;
          m_tvalid <= 1'b1;
          skid_valid <= 1'b0;
          s_tready   <= 1'b1;
        end else begin
          m_tdata  <= s_tdata;
          m_tlast  <= s_tlast;
          m_tvalid <= s_tvalid;
        end
      end else if (s_tvalid && s_tready) begin  // downstream stalled, save beat
        skid_data  <= s_tdata;
        skid_last  <= s_tlast;
        skid_valid <= 1'b1;
        s_tready   <= 1'b0;
      end
    end
  end
endmodule

Use Cases

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