AXI4 – Advanced eXtensible Interface

Overview

AXI4 (Advanced eXtensible Interface 4) is part of the AMBA 4 specification released by Arm. It is designed for high-bandwidth, low-latency on-chip communication — typically connecting high-performance masters such as CPUs, DMA engines, and GPUs to memory controllers, peripherals, and other slaves in an SoC.

The defining feature of AXI4 is its channel-based architecture. Rather than a single multiplexed bus, it uses five independent channels, each with its own VALID/READY handshake. This allows the address of the next transaction to be issued before the previous one completes, enabling pipelined and out-of-order operation.

Five Independent Channels

AXI4 separates traffic into five channels. Each operates independently with its own VALID/READY pair, so a slow response on the write response channel cannot block progress on the read address channel.

Signal Reference

Global

Write Address Channel (AW) — Master → Slave

Write Data Channel (W) — Master → Slave

Write Response Channel (B) — Slave → Master

Read Address Channel (AR) — Master → Slave

Read Data Channel (R) — Slave → Master

VALID / READY Handshake

Every AXI4 channel uses the same two-signal handshake. A transfer completes on the clock edge where both VALID and READY are HIGH simultaneously.

Write Transaction

A write transaction uses all three write channels: AW → W → B. The address and data channels can operate concurrently — the master does not need to wait for AW to complete before issuing data on W.

Steps: (1) Master drives write address on AW channel — accepted when AWVALID & AWREADY. (2) Master drives write data beats on W channel, asserting WLAST on the final beat — each beat accepted when WVALID & WREADY. (3) Slave issues write response on B channel — accepted when BVALID & BREADY.

Read Transaction

A read uses two channels: AR → R. The master sends the read address; the slave returns data beats with RLAST on the final beat. No separate response channel is needed — the per-beat RRESP carries status.

Burst Types & Attributes

The transfer size (AWSIZE / ARSIZE) encodes bytes per beat as a power of two, and must not exceed the data bus width:

Response Codes (BRESP / RRESP)

Verilog RTL — AXI4-Lite Slave (Register File)

A minimal AXI4-Lite slave with a 4×32-bit register file. AXI4-Lite is the simplified subset (no bursts), widely used for control register access.

module axi4lite_slave #(
  parameter AW = 32,
  parameter DW = 32
) (
  input  wire          ACLK, ARESETn,

  // Write address channel
  input  wire [AW-1:0] AWADDR,
  input  wire          AWVALID,
  output reg           AWREADY,

  // Write data channel
  input  wire [DW-1:0] WDATA,
  input  wire [DW/8-1:0] WSTRB,
  input  wire          WVALID,
  output reg           WREADY,

  // Write response channel
  output reg  [1:0]    BRESP,
  output reg           BVALID,
  input  wire          BREADY,

  // Read address channel
  input  wire [AW-1:0] ARADDR,
  input  wire          ARVALID,
  output reg           ARREADY,

  // Read data channel
  output reg  [DW-1:0] RDATA,
  output reg  [1:0]    RRESP,
  output reg           RVALID,
  input  wire          RREADY
);

  // 4-register file
  reg [DW-1:0] regs [0:3];
  reg [AW-1:0] aw_addr_lat;
  integer i;

  // ── Write path ──────────────────────────────
  always @(posedge ACLK) begin
    if (!ARESETn) begin
      AWREADY <= 1'b0; WREADY <= 1'b0;
      BVALID  <= 1'b0; BRESP  <= 2'b00;
      for (i=0; i<4; i=i+1) regs[i] <= 32'h0;
    end else begin
      // Accept write address
      AWREADY <= AWVALID && !AWREADY;
      if (AWVALID && AWREADY)
        aw_addr_lat <= AWADDR;

      // Accept write data and update register
      WREADY <= WVALID && !WREADY;
      if (WVALID && WREADY) begin
        if (aw_addr_lat[3:2] < 4) begin
          if (WSTRB[0]) regs[aw_addr_lat[3:2]][7:0]   <= WDATA[7:0];
          if (WSTRB[1]) regs[aw_addr_lat[3:2]][15:8]  <= WDATA[15:8];
          if (WSTRB[2]) regs[aw_addr_lat[3:2]][23:16] <= WDATA[23:16];
          if (WSTRB[3]) regs[aw_addr_lat[3:2]][31:24] <= WDATA[31:24];
          BRESP <= 2'b00; // OKAY
        end else
          BRESP <= 2'b10; // SLVERR
        BVALID <= 1'b1;
      end

      // Clear response once master accepts it
      if (BVALID && BREADY)
        BVALID <= 1'b0;
    end
  end

  // ── Read path ───────────────────────────────
  always @(posedge ACLK) begin
    if (!ARESETn) begin
      ARREADY <= 1'b0; RVALID <= 1'b0;
      RDATA   <= 32'h0; RRESP  <= 2'b00;
    end else begin
      ARREADY <= ARVALID && !ARREADY;
      if (ARVALID && ARREADY) begin
        RDATA  <= (ARADDR[3:2] < 4) ? regs[ARADDR[3:2]] : 32'hDEAD_BEEF;
        RRESP  <= (ARADDR[3:2] < 4) ? 2'b00 : 2'b10;
        RVALID <= 1'b1;
      end
      if (RVALID && RREADY)
        RVALID <= 1'b0;
    end
  end

endmodule

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