I2C – Inter-Integrated Circuit
I2C is a two-wire serial bus invented by Philips (now NXP) that lets multiple masters and multiple slaves share a single pair of lines. Its open-drain bus structure, built-in addressing, and ACK/NACK handshake make it the go-to interface for sensors, EEPROMs, RTCs, and display drivers — anywhere you need a low-pin-count, multi-device bus.
Overview
I2C (Inter-Integrated Circuit, often pronounced "I-squared-C") was designed in 1982 for connecting slow peripheral ICs to a processor using the fewest possible wires. The defining constraint — only two wires for any number of devices — shapes every design decision in the protocol.
Because all devices share the same two lines, I2C solves the "who talks when" problem through a built-in addressing scheme: every transaction begins with the master broadcasting a 7-bit (or 10-bit) slave address, and only the matching slave responds. The bus is half-duplex — the master and slave take turns driving SDA, they never transmit simultaneously. Unlike SPI, there is no separate chip-select wire; addressing replaces it.
Two-wire simplicity has a cost: I2C is slower than SPI (max 3.4 MHz vs tens of MHz for SPI), and the protocol overhead (START, address, ACK, STOP) adds latency to every transaction. For bulk data transfers, SPI wins. For configuration registers and sensor reads across many devices, I2C wins.
Signals & Open-Drain Bus
| Signal | Full Name | Direction | Description |
|---|---|---|---|
| SDA | Serial Data | Bidirectional | Carries all data: addresses, data bytes, and ACK bits. The current bus owner drives SDA; receivers listen. |
| SCL | Serial Clock | Master → Slave (normally) | Clock generated by the master. Slaves can hold SCL low to pause the master (clock stretching). Normally driven by master only. |
Open-drain and pull-up resistors
Both SDA and SCL are open-drain (or open-collector) lines. This means devices can only pull the line LOW — they cannot actively drive it HIGH. Instead, a pull-up resistor (typically 4.7 kΩ for 100 kHz, 2.2 kΩ for 400 kHz) connects each line to VCC, passively pulling it HIGH when no device is pulling it LOW.
This is crucial for two reasons:
- No bus contention: If two devices simultaneously try to drive a logic 1 vs logic 0, the open-drain line simply goes LOW (the puller wins). No device is damaged. This is what makes multi-master arbitration safe.
- Wired-AND behaviour: The line is HIGH only when every device releases it. Any single device can pull it LOW. This is used for clock stretching and arbitration.
Pull-up resistor sizing matters: Too large (e.g. 10 kΩ) → slow rise times, corrupted bits at higher speeds. Too small (e.g. 1 kΩ) → excessive current draw and marginal drive strength. Always calculate R based on bus capacitance and target speed. The I2C spec defines maximum rise times that back-calculate the minimum pull-up value.
START and STOP Conditions
I2C has no separate chip-select wire. Instead, it uses special patterns on SDA that can only occur while SCL is HIGH — something that never happens during normal data transfer. These are the START and STOP conditions.
| Condition | Symbol | What happens | Effect |
|---|---|---|---|
| START | S | SDA falls LOW while SCL is HIGH | Marks the beginning of every transaction. All slaves watch for this. |
| STOP | P | SDA rises HIGH while SCL is HIGH | Releases the bus. Slaves reset their state machines. |
| Repeated START | Sr | Another START without a preceding STOP | Changes direction (write → read) or addresses a different slave without releasing the bus. |
During normal data transfer, SDA is only allowed to change while SCL is LOW. This rule makes START and STOP instantly recognisable — they are the only events where SDA changes while SCL is HIGH.
SDA (teal) changes only when SCL (indigo) is LOW — except at START where SDA falls while SCL is HIGH, and at STOP where SDA rises while SCL is HIGH.
Data Frame & Bit Transfer
Every byte transferred on I2C (whether it is an address byte or a data byte) uses the same 9-bit frame: 8 data bits followed by 1 acknowledgement bit.
- Bits 1–8: Data, MSB first. The current driver (master or slave) holds SDA stable during each SCL HIGH pulse.
- Bit 9 (ACK/NACK): The receiver takes control of SDA. It pulls SDA LOW for ACK, or releases SDA (HIGH) for NACK.
The key rule: SDA must be stable (not changing) for the entire duration of each SCL HIGH pulse. The receiver samples SDA at each rising edge of SCL. Transitions on SDA are only allowed while SCL is LOW.
Every byte gets an ACK. After 8 data bits, the transmitter always releases SDA and generates the 9th clock pulse. The receiver pulls SDA LOW to confirm receipt. If the receiver fails to acknowledge (NACK), the master must either repeat the byte, send a STOP, or take corrective action — the protocol does not retry automatically.
Addressing
The first byte after every START is always the address byte. It identifies which slave should respond to this transaction.
7-bit addressing (most common)
The address byte contains a 7-bit slave address followed by a 1-bit R/W flag:
With 7-bit addressing, the bus can address up to 128 devices — though a handful of addresses are reserved. The most used reserved addresses are:
| Address | Reserved for |
|---|---|
| 0x00 | General Call — all slaves respond (write only) |
| 0x01 | CBUS compatibility |
| 0x02–0x03 | Reserved for future use |
| 0x04–0x07 | Reserved |
| 0x78–0x7F | 10-bit address extension prefix |
10-bit addressing
For large systems needing more than 112 usable addresses, I2C supports 10-bit addressing using a two-byte sequence:
11110XXMSB 2 bits + 10-bit prefixThe prefix 11110 in the first byte signals to all slaves that this is a 10-bit address. A 10-bit read transaction adds a Repeated START after the address phase.
ACK and NACK
After every 8-bit byte, the transmitter releases SDA (stops driving it). The receiver then drives the 9th bit:
| 9th bit | Name | SDA state | Driven by | Meaning |
|---|---|---|---|---|
| ACK | Acknowledge | LOW | Receiver pulls SDA down | "Byte received successfully, continue." |
| NACK | Not Acknowledge | HIGH | Receiver releases SDA (pull-up holds it high) | "Stop sending" or "I'm busy" or "address not recognised." |
When does the master send NACK? During a read transaction, the master sends NACK after the last byte it wants to receive. This signals "I have enough data, stop." If the master sends ACK, the slave knows to prepare and send the next byte. If the master sends NACK, the slave releases the bus and the master follows with a STOP.
Write Transaction
A write transaction sends data from master to slave. The master drives SDA for both the address byte and every data byte. The slave only drives SDA during the ACK bits.
Step-by-step:
- START — Master pulls SDA LOW while SCL is HIGH. All slaves detect this and begin listening.
- Address + W bit — Master sends 7-bit address with R/W = 0 (write). All slaves compare the address to their own.
- Slave ACK — The matching slave pulls SDA LOW during the 9th clock pulse. Unmatched slaves ignore the rest of the transaction.
- Data byte(s) — Master sends one or more data bytes, MSB first. After each byte, the slave ACKs.
- STOP — Master raises SDA while SCL is HIGH, releasing the bus.
A practical example: writing the value 0x72 to register 0x01 of a sensor at address 0x48 — the master sends three bytes: 0x90 (0x48 shifted left + W=0), 0x01 (register address), 0x72 (value). Each byte is followed by a slave ACK.
Read Transaction
A read transaction receives data from slave to master. After the address byte (with R/W = 1), the slave takes control of SDA and drives all subsequent data bytes. The master only drives SDA for the ACK/NACK bits.
Step-by-step:
- START — Master initiates the transaction.
- Address + R bit — Master sends 7-bit address with R/W = 1 (read).
- Slave ACK — Matching slave acknowledges. It then takes control of SDA to send data.
- Data bytes — Slave drives SDA with each byte. Master ACKs each byte it successfully receives.
- Master NACK on last byte — When the master has received all the bytes it needs, it sends NACK instead of ACK. This tells the slave to stop.
- STOP — Master releases the bus.
Direction switch on SDA: After the slave ACKs the address byte (slave drives SDA LOW), the slave must continue holding SDA and begin driving the first data byte. The master releases SDA at exactly this point. Timing this switch is critical — both devices must not drive SDA simultaneously.
Combined Transaction (Repeated START)
Many real devices require you to write a register address, then immediately read from it — without releasing the bus in between. Releasing the bus (STOP) would allow another master to steal it, and some devices reset their internal pointer on STOP.
The solution is the Repeated START (Sr): instead of sending STOP after the write phase, the master sends a new START condition directly. This changes direction (write → read) while keeping the bus locked.
This combined pattern is extremely common. Reading a temperature from a sensor (e.g., LM75, BME280), fetching a byte from an EEPROM, or reading a gyroscope register — all use this write-address then read-data sequence with a Repeated START.
The bus stays locked from the initial START to the final STOP. Other masters on the bus must wait. If you do not need to hold the bus between the write and read, it is equally valid (and simpler) to use STOP followed by a new START.
Clock Stretching
A slow slave can pause the master using clock stretching: after a SCL falling edge, the slave holds SCL LOW (using its open-drain output) before releasing it. The master, which monitors SCL, sees that SCL has not risen as expected and waits.
Clock stretching is used when a slave needs extra time — for example, an ADC completing a conversion, or an EEPROM performing an internal write. The master cannot force the clock; it must wait. This is another feature that requires the SCL line to be open-drain: the slave needs to actively hold the line LOW, and the master must be able to detect this (rather than both driving the line to different levels).
Not all masters support clock stretching. Some low-cost microcontroller I2C peripherals use a strict timing model and will generate an error if SCL is not released within the expected window. Always check whether your master controller handles clock stretching before using a slave that uses it.
Speed Modes
| Mode | Max Clock | Typical Pull-up | Notes |
|---|---|---|---|
| Standard Mode (Sm) | 100 kHz | 4.7 kΩ | Original spec. Compatible with all I2C devices. Long traces, high capacitance tolerance. |
| Fast Mode (Fm) | 400 kHz | 2.2 kΩ | Most common in modern designs. Smaller pull-ups needed for rise time. Backward compatible. |
| Fast-Mode Plus (Fm+) | 1 MHz | 1 kΩ or active pull-up | Requires stronger drivers. Devices must declare Fm+ support. Increasing adoption. |
| High-Speed Mode (Hs) | 3.4 MHz | Active current source | Requires current-source pull-ups and special Master Code handshake. Rarely used. |
| Ultra Fast-Mode (UFm) | 5 MHz | Push-pull (no pull-up) | Unidirectional only — no ACK, no clock stretching. Very uncommon. |
All modes below Hs are backward compatible — a 400 kHz master can communicate with 100 kHz slaves at 100 kHz. High-Speed mode requires a special startup sequence and is mainly found in memory devices.
I2C vs SPI
| Feature | I2C | SPI |
|---|---|---|
| Wires | 2 (SDA + SCL) | 4 + 1 CS per slave |
| Duplex | Half-duplex (shared SDA) | Full-duplex (separate MOSI + MISO) |
| Max speed | 3.4 MHz (Hs) | Tens of MHz (device-limited) |
| Slave select | Address in-band (no extra pin) | Dedicated CS_N pin per slave |
| Multi-slave | Yes — up to 112 (7-bit) on same 2 wires | Yes — one CS pin per slave |
| Multi-master | Yes — with arbitration | No — single master only |
| ACK / error detect | Built-in per byte | None — application layer |
| Protocol overhead | START, address, ACK, STOP per transaction | Only CS assertion / deassertion |
| Best for | Many low-speed peripherals, sensors, EEPROMs | High-speed single slave — flash, ADC, display |